M13L32321A-2G Datasheet, PDF (31/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
Timing Diagram
M13L32321A (2G)
Basic Timing (Setup, Hold and Access Time @ BL=4, CL=2)
CLK
CLK
CKE
0
1
2
3
4
5
6
7
8
9
10
tCH tCL
tCK
HIGH
tCH tCL
tCK
CS
RAS
tIS
tIH
CAS
BA
A8/AP
Ra
ADDR
(A0~A7, A9)
Ra
WE
DQS
DQ
DM
COMMAND
ACTIVE
Ca
Cb
tDQSCK
tRPRE
tDQSCK
tRPST
Hi-Z
tDQSQ
tLZ
tAC _tHZ
Qa0 Qa1 Qa2 Qa3
tWPRES
Hi-Z
tQH
tDQSS
tDQSL
tDQSH
tWPRE
tDS tDH tDS tDH
tWPST
Db0 Db1 Db2 Db3
Hi-Z
Hi-Z
READ
WRITE
: Don’t care
11101 B3 2R .A
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2012
Revision : 1.0
31/48