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| M13L32321A-2G Datasheet, PDF (47/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle | |||
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ESMT
Revision History
Revision
1.0
Date
2012.10.18
Original
M13L32321A (2G)
Description
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2012
Revision : 1.0
47/48
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