M13L32321A-2G Datasheet, PDF (38/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
Write Interrupted by a Read (@ BL=8, CL=2)
0
1
2
3
4
5
CLK
CLK
CKE
HIGH
CS
RAS
CAS
BA
A8/AP
ADDR
(A0~A7, A9)
Ca
Cb
WE
DQS
DQ
DM
COMMAND
Da0 Da1 Da2 Da3 Da4 Da5
WRITE
tWTR
READ
M13L32321A (2G)
6
7
8
9
10
Qb0 Qb1 Qb2 Qb3 Qb4 Qb5 Qb6 Qb6
: Don’t care
111 0 1 B 3 2 R . A
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2012
Revision : 1.0
38/48