M13L32321A-2G Datasheet, PDF (15/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
M13L32321A (2G)
Extended Mode Register Set (EMRS)
The extended mode register stores the data enabling or disabling DLL and selecting output drive strength. The default value of the
extended mode register is not defined, therefore the extended mode register must be written after power up for enabling or disabling
DLL. The extended mode register is written by asserting low on CS , RAS , CAS , WE and high on BA (The DDR SDRAM
should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins
A0~A10 and BA in the same cycle as CS , RAS , CAS and WE going low is written in the extended mode register. Two clock
cycles are requested to complete the write operation the mode register. The mode register contents can be changed using the same
command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or
disable. A1 and A6 are used for setting drive strength. “High” on BA is used for EMRS. All the other address pins except A0~1, A6
and BA must be set to low for proper EMRS operation. Refer to the table for specific codes.
BA
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
1
RFU
DS
RFU
DS DLL
Extended Mode Register
A6 A1
0
0
0
1
1
0
1
1
BA Operating Mode
0
MRS Cycle
1
EMRS Cycle
Driver Strength
100% Strength
60% Strength
15% Strength
30% Strength
A0 DLL Enable
0
Enable
1
Disable
Note: RFU (Reserved for future use) must stay “0” during EMRS cycle.
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2012
Revision : 1.0
15/48