M13L32321A-2G Datasheet, PDF (37/48 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
Write Interrupted by Precharge & DM (@ BL=8)
0
1
CLK
CLK
CKE
2
3
4
0
HIGH
CS
RAS
CAS
BA
A8/AP
ADDR
(A0~A7, A9)
Ca
WE
M13L32321A (2G)
1
2
3
4
5
Cb
Cn
DQS
DQ
DM
COMMAND
Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7
Db0 Db1 Dn0 Dn1 Dn2 Dn3
WRITE
PRE
CHARGE
tCCD
WRITE
WRITE
: Don’t care
1110 1B 3 2R .A
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2012
Revision : 1.0
37/48