S1L60000 Datasheet, PDF (57/230 Pages) Epson Company – GATE ARRAY

Chapter 4: Input/Out Cells Buffers and Their Use
Input
Level
CMOS
Table 4-13 Gated Bi-directional Cell List
(AND Type, V_DD = 2.5 V, 2.0 V)
Drain
Type
Test
Function*²
Output
Latch
Function
Speed
Output
Current
(mA)*¹
Without
Resistor
Pull Down *¹
50 kΩ 100 kΩ
Pull Up *¹
50 kΩ 100 kΩ
-3/3
BA1T BA1D1T BA1D2T BA1P1T BA1P2T
-6/6
Normal
-9/9
BA2T
BA3T
BA2D1T BA2D2T BA2P1T BA2P2T
BA3D1T BA3D2T BA3P1T BA3P2T
Normal Exist
Non-
exist
High
Speed
-18/18
-9/9
-18/18
BA4T
BA3AT
BA4AT
BA4D1T BA4D2T BA4P1T BA4P2T
BA3AD1T BA3AD2T BA3AP1T BA3AP2T
BA4AD1T BA4AD2T BA4AP1T BA4AP2T
Low
Noise
-9/9
-18/18
BA3BT BA3BD1T BA3BD2T BA3BP1T BA3BP2T
BA4BT BA4BD1T BA4BD2T BA4BP1T BA4BP2T
*1: The value at V_DD = 2.5 V
*2: In addition to the configurations in Table 4-13, the gated bi-directional buffers may be configured which do not
have test pins. Customers desiring to use such structures should direct inquiries to EPSON.
Input
Level
CMOS
Table 4-14 Gated Bi-directional Cell List
(OR Type, V_DD = 2.5 V, 2.0 V)
Drain
Type
Test ^Output
Function*²
Latch
Function
Speed
Output
Current
(mA)*¹
Without
Resistor
Pull Down *¹
50 kΩ 100 kΩ
Pull Up *¹
50 kΩ 100 kΩ
-3/3
BO1T BO1D1T BO1D2T BO1P1T BO1P2T
-6/6
Normal
-9/9
BO2T BO2D1T BO2D2T BO2P1T BO2P2T
BO3T BO3D1T BO3D2T BO3P1T BO3P2T
Normal Exist
Non-
exist
High
Speed
-18/18
-9/9
-18/18
BO4T
BO3AT
BO4AT
BO4D1T BO4D2T BO4P1T BO4P2T
BO3AD1T BO3AD2T BO3AP1T BO3AP2T
BO4AD1T BO4AD2T BO4AP1T BO4AP2T
Low
Noise
-9/9
-18/18
BO3BT BO3BD1T BO3BD2T BO3BP1T BO3BP2T
BO4BT BO4BD1T BO4BD2T BO4BP1T BO4BP2T
*1: The value at V_DD = 2.5 V
*2: In addition to the configurations in Table 4-14, the gated bi-directional buffers may be configured which do not
have test pins. Customers desiring to use such structures should direct inquiries to EPSON.
50
EPSON
GATE ARRAY S1L60000 SERIES
DESIGN GUIDE