S1L60000 Datasheet, PDF (19/230 Pages) Epson Company – GATE ARRAY

Chapter 1: Overview
The process flow of the gate array development process is shown below:
Customer
Product Plan
Functional Spec.
Distributor (Interface)
EPSON
Circuit Design
Test Pattern
Design
Logical Check
(Simulation)
NG _Verification
NG _Verification
OK
NG
Check
OK
NG
Check
OK
ES(TS) Approve
the Prototype
Approve
Delivery Spec
G/A development
request
Simulation
file
*Schematic
*Pin Assinment
*Timing wave form
*Marking diagram
*P/O
Simulation list
Delay Analizing
Timing Check
(Simulation)
NG
Verification*
OK
Place & Rout
Delay Analizing
Post Simulation
Customer Spec
(Sign off)
Make Masks
TS (Test Sample)
fabrication
ES (Engineering
Sample) fabrication
ES(TS) Prototype
Approval
Delivery Spec
Delivery Spec
Approval
MP Setup
Delivery Spec.
publication
MP
( ) is based on customer’s requirement.
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EPSON
GATE ARRAY S1L60000 SERIES
DESIGN GUIDE