S1L60000 Datasheet, PDF (37/230 Pages) Epson Company – GATE ARRAY

Chapter 3: Cautions and Notes Regarding Circuit Design
(7) Logic circuit design rule for ATPG (DFT)
To operate ATPG, the logic circuits should be scanned. According to the following rules,
the original circuits that are observed to check very well should be designed. The following
contents show a concrete example, so please contact EPSON Sales division if logic circuit
design has difficulty handling the ATPG design.
• Only one pin is needed for the dedicated pin used as the scan enable pin (SCANEN).
• Please send the trial data to EPSON about a week before sending the formal data.
EPSON will check the trial data of the logic circuit before getting the formal data. The
process after obtaining the formal logic circuit data should be highly efficient and the
fault detection rate of the logic circuit must go up.
• The clock, setting and resetting to the scan data in all of FF scanned must be
controlled directly at the external pin.
➝ If they cannot be controlled, use the ATPG test pin (ATPGEN) separated from the
SCANEN pin and design the logic circuit so that it can be controlled.
➝ When the logic circuit is configured to input multiple clocks from the external pin,
the ATPGEN pin should be designed to be operated again in the active state by
inputting only one clock for all FF scanned. However, if there is only one circuit,
please contact EPSON sales division about the multiple circuits in this case.
LOGIC
CLK
ATPGEN
IBC
CRBF✽
AO24A
IBCD1
Figure 3-11 Example of Clock Line Process
DQ
DF
C XQ
DQ
DF
C XQ
• It is forbidden to design the circuit used to scan FF at the original circuit.
• Cope with the clock skew of clock nets by using Clock Tree Synthesis.
• Allocate I/O cells at the top of the hierarchical design.
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EPSON
GATE ARRAY S1L60000 SERIES
DESIGN GUIDE