S1L60000 Datasheet, PDF (21/230 Pages) Epson Company – GATE ARRAY

Chapter 2: Estimating Gate Density and Selecting the Master
2.4 Selecting the Master
Select the appropriate master from Table1-1, based on the estimated number of BCs, the
number of required input and output pins (including power supply pins) and the package to be
used.
The actual number of BCs (BC_A) which can be used for each device type is estimated using
the following formula from the gross number of BCs (BC_G) loaded on each master (shown in
Table 1-1 of the previous chapter) and the cell utilization ratio (U).
BC_A = U × BC_G
NOTE: When a RAM circuit is included, this estimate should be made after refering to the
following section and after refering to Chapter 5.
Also when a circuit is used by dual power, the estimate should be made after refering
to Chapter 11.
2.5 Estimating the BCs That Can Be Used in Circuits Which
Include RAM
RAM blocks, in comparison to MSI cells, are extremely large and have fixed shapes (defined
vertical and horizontal dimensions). Because of this, some RAM blocks which may appear to
fit on the chip because of calculations based on the number of BCs may, in actuality, not be
placable on a given master. Thus, the first decision is that of whether or not the RAM
configuration is available on a given master. Please refer to Chapter 5.
Once the masters which can accommodate the RAM have been selected, it becomes possible
to estimate the number of BCs (BC_AWR) of random logic (excluding RAM) available using the
formula below.
BC_AWR = 0.9 × U × (BC_G - BC_RAM)
where
BC_AWR is the number of BCs available for random logic
BC_G is the total BCs available on a mater (raw gates)
BC_RAM is the BC use of RAM(s) (See Chapter 5 for BC calculation)
U is the utilization ratio.
NOTE: Actual BCs available (BC_AWR) is design dependent.
Use the formula above for estimation purposes only.
Please consult EPSON for design specific information.
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EPSON
GATE ARRAY S1L60000 SERIES
DESIGN GUIDE