S1L60000 Datasheet, PDF (23/230 Pages) Epson Company – GATE ARRAY

Chapter 3: Cautions and Notes Regarding Circuit Design
3.4 Hazard Countermeasures
In circuits such as decoders and multiplexors which are structured from combinational
functions such as NAND gates or NOR gates, extremely short pulses can be produced by
differences in the gate delay times. These short pulses are called hazards, and when these
hazards propagate to clock, reset or reset pins of FF_S (Flip Flop), malfunctions may occur.
Because of this, it is necessary to use caution when designing circuits which may produce
hazards, creating circuit structures which do not propagate hazards, having decoder circuits
with “enable” terminals, etc.
3.5 Limitations on Logic Gate Output Load
With CMOS circuits, signal propagation time (t_pd) and signal rise and fall times (t_slew)
characteristically increase as load capacitance of the output increases.
Cell propagation delay is determined, in part, by the load capacitance at the output terminals.
When the load capacitance is too large, the propagation delay increases, and malfunctions
may result. Because of this, there are limitations on the number of loads which can be
connected to the output terminals of each cell, and these limitations are referred to as “fan-out
constraints”.
The input terminal capacitance of each gate differs from gate input to gate input. The input
capacitance of each gate input is defined relative to the input capacitance of an inverter
(IN1 which is defined as being equal to 1) is called the “fan-in”.
Circuits should be designed so that the sum of the fan-ins connected to the output terminals of
each gate does not exceed the fan-out constraints of that output terminal.
Also, high speed clock lines (f max = 60 MHz or more), should be designed so that the output
terminal load of the associated logic gates is about half of the fan-out constraints to ensure
high performance.
In the actual LSI circuit layout, both the input capacitance of the next-stage gate and the wiring
capacitance of a signal are applied as load capacitance. Because accurate wiring
capacitance is determined by the placement and routing of a circuit, the placement and routing
may result in the application of a large load capacitance to a specific node. The conditions of
the loads on each circuit node can be determined by the output results of tslew. Please note
that if the output of tslew exceeds the standard value, we may request circuit modification in
order to keep it within the specified limit. To control increases in the load capacitance following
the placement and routing of the circuit, the number of circuit branches within a single node
should be kept as low as possible and, if branches exist, buffers with a higher number of fan-
outs should be used.
3.6 Bus Circuits
Internal 3-state bus circuits are constructed, using 3-state logic gates. The 3-state logic gates
output terminals can be wired together if at all times one, and only one 3-state logic gate is
active at a given time (while the remaining 3-state logic gate outputs are put in high impedance
state). This circuit allows multiple signal sources to share a given net at different time intervals
during circuit operation.
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EPSON
GATE ARRAY S1L60000 SERIES
DESIGN GUIDE