S1L60000 Datasheet, PDF (110/230 Pages) Epson Company – GATE ARRAY

Chapter 6: Circuit Design Taking Testability Into Account
< Exampleof APF Format>
* ^{EXAMPLE of Test Pattern for AC & DC Test}
$RATE 200000
$RESOLUTION 0.001ns
$STROBE 185000
$NODE
$TSTEN
I0
INP0
I0
INP1
I0
INP2
I0
IA0
I0
ID0
I0
ID1
I0
ICS1
I0
ICS2
I0
IRW1
I0
IRW2
I0
BID1
B0
OUT0
O
OUT1
O
OUT2
O
OUT3
O
OUT4
O
$ENDNODE
$PATTERN
#
TIIIIIIIIIIBOOOOO
#
SNNNADDCCRRIUUUUU
#
TPPP001SSWWDTTTTT
#
E012 1212101234
#
N
#
#
IIIIIIIIIIIBOOOOO
#
U
#
#
0 00000......XXXXXX
1 10000......LLLLLX : Dedicated AC path
2 10010......LLLLHX
3 10000......LLLLLX
4 10001......LLLLLX : Dedicated AC path2 (delay pass)
5 10011......LLLLHX
6 10001......LLLLLX
7 11010......0ZHHHX : Off state leak current (bypass)
8 11010......1ZHHHX
9 10000......LLLLLX : Output characteristics
10 10100......HHHHHX
$ENDPATTERN
#
# EOF
note)
. is 1 or 0 input
Figure 6-3 Example of the generation of a test pattern when there is a test option
GATE ARRAY S1L60000 SERIES
DESIGN GUIDE
EPSON
103