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| S1L60000 Datasheet, PDF (160/230 Pages) Epson Company – GATE ARRAY | |||
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Chapter 11: Dual Power Supplies Guidelines
11.4.2.1 Input Buffers for the HVDD System
Inputs are structured from input cells alone.
The HVDD input buffers are comprised of the HVDD system circuits for the initial-stage input,
and the next-stage is comprised of LVDD system circuits. The HVDD system signals are
converted to LVDD system signals after which these signals are supplied to the MSI cells
(internal cell region). The HVDD system input buffers are as shown in Table 11-6-1 to Table 11-
7-2.
Table 11-6-1 HVDD System Input Buffers
(HVDD = 3.3 V)
Cell Name
Input Level
Function
Pull-up/Pull-down Resistors
HIBC
HIBCPâ
HIBCDâ
CMOS
CMOS
CMOS
Buffer
Buffer
Buffer
None
Pull-up Resistor (60 kâ¦, 120 kâ¦)
Pull-down Resistor (60 kâ¦, 120 kâ¦)
HIBT
HIBTPâ
HIBTDâ
LVTTL
LVTTL
LVTTL
Buffer
Buffer
Buffer
None
Pull-up Resistor (60 kâ¦, 120 kâ¦)
Pull-down Resistor (60 kâ¦, 120 kâ¦)
HIBH
HIBHPâ
HIBHDâ
CMOS Schmitt
CMOS Schmitt
CMOS Schmitt
Buffer
Buffer
Buffer
None
Pull-up Resistor (60 kâ¦, 120 kâ¦)
Pull-down Resistor (60 kâ¦, 120 kâ¦)
HIBS
HIBSPâ
HIBSDâ
LVTTL Schmitt
LVTTL Schmitt
LVTTL Schmitt
Buffer
Buffer
Buffer
None
Pull-up Resistor (60 kâ¦, 120 kâ¦)
Pull-down Resistor (60 kâ¦, 120 kâ¦)
HIBPB
HIBPBPâ
HIBPBDâ
PCI-3 V
PCI-3 V
PCI-3 V
Buffer
Buffer
Buffer
None
Pull-up Resistor (60 kâ¦, 120 kâ¦)
Pull-down Resistor (60 kâ¦, 120 kâ¦)
NOTE: When â value is 1 or 2 , the pull-up/pull-down resistance values correspond to 1:60kâ¦, 2:120kâ¦
respectively.
GATE ARRAY S1L60000 SERIES
DESIGN GUIDE
EPSON
153
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