S1L60000 Datasheet, PDF (142/230 Pages) Epson Company – GATE ARRAY

Chapter 10: Pin Layout Considerations
10.3 Cautions and Notes Regarding the Layout of pins
Once the package to be used has been selected, then it is time to layout the pins. Please see
the specific “Pin Layout Table” regarding the number of power supply pins and useable input/
output pins in the various S1L60000 Series Packages.
Once the pin layout has been established, submit to EPSON a pin assignment specification
which has been filled out with the pin layout. EPSON will layout the interconnections
according to the specification submitted by the customer, so we request that the customer
carefully check this specification.
Please request the specific “Pin Layout Table” from our sales staff.
The pin layout is one of the critical specifications which controls the quality of the LSI. It is
especially important in avoiding malfunctions due to noise. Moreover, problems with noise are
difficult to check for in simulations. So that there will be are no malfunctions with non-
traceable causes in the customer’s LSI, we urge the customer to carefully study the guidelines
detailed in this chapter before generating the pin layout.
10.3.1 Fixed Power Supply Pins
There are some pins which can only be used for power supply, depending on the combination
of each device and package in this series. Because there are some pins which must be set to
V_DD pins and some pins which must be set to V_SS pins please consult with EPSON when
selecting a package.
10.3.2 Cautions and Notes Regarding the Pin Layout
The pin layout influences the logical functioning and electrical characteristics of the LSI.
Moreover, the pin layout may be constrained by the construction of the LSI, the structuring of
the cells and the bulk, etc. Because of this, we will explain factors which must be researched
when creating the pin layout, factors such as the power supply current, the input pin/output pin
isolation, the critical signals, the pull-up/pull-down resistor inputs, simultaneous output, current
drivers, etc.
(1) Power Supply Currenµt (I_DD, I_SS)
When it comes to the power supply current (I_DD, I_SS) there are limitations on the tolerable
levels for current from the power supply through the power supply pins when in an
operating state. When the tolerable levels are exceeded, the current density within the
power supply interconnects within the LSI becomes too high, and the voltage generated by
the current and the resistance within the interconnects increases or decreases. This may
lead to malfunctioning and may have an impact on DC or AC characteristics.
In order to avoid these types of problems, it is necessary to reduce the current density and
the power supply interconnect line impedance. To do this, it is necessary to estimate the
power consumption during the design of the gate array, and to make sure that there are
enough power supply pins so that the current through each of the power supply pins does
not exceed tolerances. Moreover, the layout should be such that the power supply pins
are not concentrated all in one location, but rather are spread out. See Section 10.1,
“Estimating the Number of Power Supply Pins” about number of power supply pins.
GATE ARRAY S1L60000 SERIES
DESIGN GUIDE
EPSON
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