S1L60000 Datasheet, PDF (54/230 Pages) Epson Company – GATE ARRAY

4.3 Oscillation Circuit
Chapter 4: Input/Out Cells Buffers and Their Use
4.3.1 Oscillation Circuit Configurations
Oscillation circuits should be configured, as shown in Figure 4-5. Both standard and gated
oscillation circuit configurations are supported as shown.
G
X
LIN
PAD
Oscillation
Inside of IC
Rf
X
D
A
LOT
PAD
G
E
X
LIN
PAD
Enable
Oscillation
Inside of IC
Rf
X
D
A
LOT
PAD
Rd
Rd
X'tal
Cg
Cd
X'tal
Cg
Cd
(a) Oscillation circuit without Enable
(b) Oscillation circuit with
Figure 4-5 Method of Structuring the Oscillator
4.3.2 Oscillation Circuit Considerations
(1) Pin Layout
For the QFP package, follow the rules for pin layout described below. For other packages,
please contact to our sales office for the necessary information on pin layout.
• The inputs and outputs of the oscillation circuits should be positioned on adjacent pins,
and should be located between power supply pins (V_DD, V_SS).
• Do not locate high drive output pins near the input/output pins of the oscillation circuit.
Be especially careful to locate any outputs having the same phase or the opposite phase
of the oscillating wave form as far as possible from the oscillation circuit input/output
pins.
• Whenever possible, locate the input/output pins of the oscillation circuit near the center
of the edge of the package.
(2) Oscillation Cell Selection Criteria
The frequency at which oscillation is possible is approximately several 10 KHz to mega
hertz(MHz). For details, please direct inquiries to EPSON.
GATE ARRAY S1L60000 SERIES
EPSON
47
DESIGN GUIDE