S1L60000 Datasheet, PDF (173/230 Pages) Epson Company – GATE ARRAY

Chapter 12: RAM (Clock Synchronous Type)
12.5 Functional Description
12.5.1 1-port RAM (Clock Synchronous Type)
(1) Input/output signals and block diagram
Table 12-5 Signal Description of a 1-port RAM (Clock Synchronous Type)
Input/output signal
Symbol
Name
CK
Clock input
XCS
XWE
A0 – An
D0 – Dn
Chip select
Write enable
Address input
Data input
Y0 – Yn
Data output
Description
The rising edge (L(H) on the clock input (CK) latches chip select
(XCS), write enable (XWE), address inputs (A0-An), and data inputs
(D0-Dn) into the internal logic of the RAM.
Latched by the rising edge on the clock input (CK). When XCS is
latched low, chip select is enabled.
Latched by the rising edge on the clock input (CK). When XWE is
latched low, write is enabled; when high, read is enabled.
Latched by the rising edge on the clock input (CK).
Latched by the rising edge on the clock input (CK). The data is
written into memory cells when write enable (XWE) = low.
During readout, the data from memory cells are output after a
specified access time has elapsed from the rising edge on the clock
input (CK). During write, the write data is output from these pins
synchronously with the CK. Therefore, note that during the writing of
data, previously read data is not retained.
Figure 12-1 Block Diagram of a 1-port RAM (Clock Synchronous Type)
An
A2 A1
Address Buffer
Row Decoder
Control
CK
A0
XCS
XWE
Memory Cell Array
Memory Cell Array
Data I/O Buffer
D0
Y0
Data I/O Buffer
D1
Y1
166
Memory Cell Array
Data I/O Buffer
Dn
Yn
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