S1X70000 Datasheet, PDF (362/379 Pages) Epson Company – STANDARD CELL / EMBEDDED ARRAY

Chapter 8 Circuit Design that Takes Testability into Account
Macro
Macro
clock
（a）
ATPGEN
ATPG mode: ATPGEN = 1
（b）
Figure 8-20 Example of Macro Cell Processing
g. Internal bus [Recommended]
Do not use bus circuits comprised of internal 3-state cells. Rather, we recommend
that the circuit be designed using selector logic. When using said bus circuits, make
sure they are fixed in such a way that the bus lines are not switched over and only one
line is activated in ATPG run mode. (If bus circuits are used, the fault-detection rate
decreases, as such circuits have fixed values.)
h. External cells with various controls [Essential]
Some types of external input and external bi-directional cells available in the
S1K70000 series come equipped with various control pins. These pins must be fixed
using the ATPG enable input pin. Follow the procedure described below to process
these pins.
• Pull-up/pull-down control pin (PC pin)
Fix this pin to the off state using the ATPG enable input pin (ATPGEN).
(PC = 1 when ATPGEN = active)
• Gating signal (C pin)
Fix this pin to the through state using the ATPG enable input pin (ATPGEN).
(C = 1 when ATPGEN = active)
i. Other
• Approximately 7 days are required for scan work (scan insertion to verification) at
Epson after netlists created in accordance with the design rules are received.
• In scan design, optimization by CTS is essential. Please make sure the Clock Tree
Synthesis Checksheet attached in Section 7.3, “Clock Tree Synthesis,” is included
with the netlists presented to Epson.
354
EPSON
STANDARD CELL S1K70000 SERIES
EMBEDDED ARRAY S1X70000 SERIES