S1X70000 Datasheet, PDF (356/379 Pages) Epson Company – STANDARD CELL / EMBEDDED ARRAY

Chapter 8 Circuit Design that Takes Testability into Account
8.7.3 Design Rules
The following section describes the design rules to be followed in order for the scan service
to be used. If the desired fault-detection rate is 90% or higher, make sure all of the
contents described herein are reflected in your design. In addition, when interfacing
your design to Epson, make sure it is accompanied by the Scan Design Checksheet
attached at the end of this chapter.
a. Scan external pins
For the circuit to be scanned, all of the external pins described below are required.
• Scan-enable input pin (SCANEN) [Dedicated pin]
This dedicated external input pin selects between the ordinary data path (parallel
operation) and the scan path (shift operation). It cannot be shared with ordinary
functions or other mode functions. Provide an input cell and external pin in the
design for use as a dedicated external pin.
• Scan-data input pins [Shareable]
These external input pins are used to set data in the scan registers that have been
incorporated into the design by scan. There must be several instances of these
input pins corresponding to the number of scan registers. Prepare one input pin
for every 300 to 500 scan registers. As many of these input pins as the number of
scan-data output pins are required.
These pins may be shared with external input pins that are used in normal
operation. However, clock pins, asynchronous set/reset pins, and analog signal
input pins cannot be used. Note that if any pin is shared, fan-out in its net
increases. Avoid sharing pins for critical paths.
The scan-data input pins are connected to the external pins at Epson during scan
of the design. Please specify the external input pin names that can be used for
this connection. Unless specified, pin assignments will be made by Epson.
• Scan-data output pins [Shareable]
These external output pins are used to output the observation data from the scan
registers that have been incorporated into the design by scan. There must be
several instances of these output pins corresponding to the number of scan
registers. Prepare one output pin for every 300 to 500 scan registers. As many of
these output pins as the number of scan-data input pins are required.
These pins may be shared with external output pins that are used in normal
operation (two-state output pins are recommended). However, analog signal
output pins cannot be used. Note that if any pin is shared, the number of cell
stages in its net increases. Avoid sharing pins for critical paths.
The scan-data output pins are connected to the external pins at Epson when the
design is scanned. Please specify the external output-pin names that can be used
for this connection. Unless specified, pin assignments will be made by Epson.
• Scan clock input pin [Same as an ordinary clock or dedicated pin]
This clock input pin is used in the test patterns generated by ATPG. Because
Epson scan cells employ the MUX scan type, this clock input pin must generally be
the same system clock used in normal operation. However, if an internally
generated clock exists, a dedicated clock pin for scan use may be required. For
details, refer to paragraph b, “Clock design,” discussed later in this section.
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EPSON
STANDARD CELL S1K70000 SERIES
EMBEDDED ARRAY S1X70000 SERIES