S1X70000 Datasheet, PDF (339/379 Pages) Epson Company – STANDARD CELL / EMBEDDED ARRAY

Chapter 8 Circuit Design that Takes Testability into Account
8.4.2 High-Density-Type 1-Port RAM
For high-density-type 1-port RAM, as for Basic-cell-type RAM, please incorporate a test
circuit which can be accessed directly from external pins and create test patterns in both
normal and test states. (Epson will use the test-state test patterns as templates as it
creates dedicated RAM test patterns.) (For details, refer to Section 8.4.1,
“Basic-Cell-Type RAM.”)
When creating test-state test patterns for high-density-type 1-port RAM, please follow the
prescribed procedure.
• Timing chart
(1) Dummy event
(2) Write event
(3) Read event
t₀
A[n:0]
D[m:0]
CK
XCS
t₁
t₂
XW E
Y[m:0]
old data(don't care)
write through data
valid data
Strobe
t₃
Recommended values for t₀–t₃: t₀ = 200ns, t₁ = 20 ns, t₂ = 100 ns, t₃ = 185 ns
• Example for APF format (16 words x 4 bits)
$RATE 200000
$STROBE 185000
$RESOLUTION 0.001ns
$NODE
IA3 I 0
IA2 I 0
IA1 I 0
IA0 I 0
ICK P 20000 120000
IXCS I 0
IXWE I 0
ID3 I 0
ID2 I 0
ID1 I 0
ID0 I 0
･･･
OY3 O
OY2 O
OY1 O
OY0 O
$ENDNODE
$PATTERN
#
AAAACXXDDDD･･･YYYY
#
3210KCW3210･･･3210
#
SE
0 00000010000･･･XXXX
1 0000P100000･･･XXXX
2 0000P110000･･･LLLL
3 01010010101･･･XXXX
4 0101P100101･･･XXXX
5 0101P110101･･･LHLH
6 11110011111･･･XXXX
7 1111P101111･･･XXXX
8 1111P111111･･･HHHH
$ENDPATTERN
Be sure to write all I/O pins to ensure that simulations
are performed.
(1) Access the test pattern for the dummy, write, and read
events in one operation (one tester cycle) and perform
the test three times: first the lower address, then the
middle address, then the upper address.
(2) Set the address and data at the beginning of a dummy
event, write the data in a write event, and read the data
in a read event.
(3) Apply CK as a pulse (RZ waveform).
(4) Change the write data after each access operation.
(5) If there is a test-mode setup sequence, be sure to insert it
prior to event 0. (Event numbers need to be reassigned.)
(6) After creating a test pattern, always confirm its
functionality through logic simulation. When simulated,
the test pattern will produce an output during a dummy
event (old data) and an output during a write event
(write-through data). However, because these outputs
do not need to be verified, we recommend that they be
rewritten to indeterminate values before being interfaced
to the tester.
Figure 8-7 Procedure for Creating Test Patterns for High-density-type 1-port RAM
STANDARD CELL S1K70000 SERIES
EMBEDDED ARRAY S1X70000 SERIES
EPSON
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