S1X70000 Datasheet, PDF (182/379 Pages) Epson Company – STANDARD CELL / EMBEDDED ARRAY

Chapter 5 Memory Blocks
An
A1
A0
CK
XCS
XWE
Control
Memory Cell Array
Column Decoder
Data I/O Buffer
Figure 5-6 Block Diagram of the High-Density Large-Capacity-Type 1-port RAM
5.5.4 Truth Table of Device Operation
For writing, assert chip select (XCS), write enable (XWE), and byte write enable
(XBWE0–XBWE3) (by pulling them Low), and set the address inputs (A0–An) and data
inputs (D0–Dn) before the clock input (CK) goes High. All of the chip-select, write-enable,
byte write-enable, address-input, and data-input signals are latched into the rising edge of
the clock input, at which time memory is activated for write operation. During this
period, the data being written is output from the data-output pins (Y0–Yn). The write
operation finishes at the fall of the clock, with the input signals unlatched and the
memory placed in standby state.
For reading, assert chip select (XCS) and deassert write enable (XWE) (by pulling XCS
Low and XWE High), and set the address inputs (A0–An) before the clock input (CK) goes
High. All of the chip-select, write-enable, and address-input signals are latched into the
rising edge of the clock input, at which time memory is activated for read operation.
During this period, data is output from the data-output pins (Y0–Yn) a finite access time
after the rise of the clock. The read operation finishes at the fall of the clock, with the
input signals unlatched and the memory placed in standby state. For either read or
write, data appears at the data-output pins even after the operation has completed and
the memory is placed in standby state.
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EPSON
STANDARD CELL S1K70000 SERIES
EMBEDDED ARRAY S1X70000 SERIES