S1X70000 Datasheet, PDF (340/379 Pages) Epson Company – STANDARD CELL / EMBEDDED ARRAY

Chapter 8 Circuit Design that Takes Testability into Account
8.4.3 High-Density-Type Dual-Port RAM
For high-density-type dual-ported RAM, as for Basic-cell-type RAM, please incorporate a
test circuit which can be accessed directly from external pins and create test patterns in
both normal and test states. (Epson will use the test-state test patterns as templates as
it creates dedicated RAM test patterns.) (For details, refer to Section 8.4.1,
“Basic-Cell-Type RAM.”)
When creating test-state test patterns for high-density-type dual-ported RAM, although
essentially the same procedure applies as is described in Section 8.4.2,
“High-Density-Type 1-Port RAM,” please follow the specific procedure described below, so
that test patterns will be created separately (depending on how the ports are used).
(1) When using as dual-ported RAM (reading and writing on both ports A and B), create
the following two test patterns:*
• Test pattern 1: Write from port A, read from port A
• Test pattern 2: Write from port B, read from port B
(2) When using as 2-port RAM (writing on port A, reading on port B), create the following
(one) test pattern.
• Test pattern 1: Write from port A, read from port B
(3) When using as 3-port RAM (reading and writing on port A, reading on port B), create
the following two test patterns:*
• Test pattern 1: Write from port A, read from port A
• Test pattern 2: Write from port A, read from port B
* To prevent possible simultaneous access of the same address, please avoid writing the
same test pattern for test patterns 1 and 2.
8.4.4 Large-Capacity-Type RAM
For large-capacity-type RAM, as for Basic-cell-type RAM, please incorporate a test circuit
which can be accessed directly from external pins and create test patterns in both normal
and test states. (The test-state test patterns become a template which Epson will use as
it creates dedicated RAM test patterns.) (For details, refer to Section 8.4.1,
“Basic-Cell-Type RAM.”)
Regarding test-state test patterns for the large-capacity-type RAM, essentially the same
procedure applies as is described in Section 8.4.2, “High-Density-Type 1-Port RAM.”
8.4.5 Mask ROM
For mask ROM, as for Basic-cell-type RAM, please incorporate a test circuit which can be
accessed directly from external pins and create test patterns in both normal and test
states. (For details, refer to Section 8.4.1, “Basic-Cell-Type RAM.”)
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EPSON
STANDARD CELL S1K70000 SERIES
EMBEDDED ARRAY S1X70000 SERIES