S1X70000 Datasheet, PDF (159/379 Pages) Epson Company – STANDARD CELL / EMBEDDED ARRAY

Chapter 5 Memory Blocks
Table 5-121 Description of High-Density-Type 1-port RAM Signals
Input/Output Signal
Symbol
Name
CK
Clock input
XCS
XWE
Chip select
Write enable
XBWEn Byte write enable
A0–An
D0–Dn
Address input
Data input
Y0–Yn
Data output
Functional Description
Chip select (XCS), write enable (XWE), byte write enable (XBWEn),
address input (A0–An), and data input (D0–Dn) are latched into the
rising edge (Low-to-High transition) of the clock input (CK).
Memory is activated when the latched chip select signal is Low.
While memory is active, data is written to memory when the latched
write-enable signal is Low, or read from memory when the signal is
High. Operation finishes on the next fall of the clock.
Latched into the rising edge of the clock input (CK). When the
latched value is Low, memory is activated.
Latched into the rising edge of the clock input (CK). Memory is
activated for write operation when the latched value is Low, or for
read operation when the latched value is High.
Latched into the rising edge of the clock input (CK). Each byte of
data is assigned one byte write-enable signal. Only data bytes with
Low byte write enable (XBWEn) when write enable (XWE) is Low,
are written to memory.
XBWE0 for D0–D7
XBWE1 for D8–D15
XBWE2 for D16–D23
XBWE3 for D24–D31
Latched into the rising edge of the clock input (CK).
The write data is latched into the rising edge of the clock input (CK)
and written to memory cells.
During reading, the data from memory cells is output a finite access
time after the rising edge of the clock input (CK). During writing,
the latched write data is output from these pins.
STANDARD CELL S1K70000 SERIES
EMBEDDED ARRAY S1X70000 SERIES
EPSON
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