S1X70000 Datasheet, PDF (346/379 Pages) Epson Company – STANDARD CELL / EMBEDDED ARRAY

Chapter 8 Circuit Design that Takes Testability into Account
2) Restrictions during normal operation
Circuits are added in the periphery of memory when memory BIST is applied, and
this peripheral circuit must be initialized in normal operation, not just in BIST mode
(unless it is initialized, the memory cannot be accessed during simulation).
Therefore, the entire circuit, including the customer’s circuit, must be configured so as
to satisfy the following initialization requirements ^(*4):
• Memory BIST can be set to MBIST_EN = 0 (normal-operation mode) and
BIST_CLK (= memory clock) can be applied to at least two pulses.
3) Skew adjustment of the memory clock
Because the memory BIST circuit (collars and controller) is comprised of multiple
sequential circuits, clock skews must be adjusted between the memory’s clock signal
and the clock signals for the internal flip-flops of the BIST circuit (collars and
controller). Therefore, make sure the clock for the memory to which memory BIST is
to be applied is designed for optimization by Clock Tree Synthesis. For more detailed
contents of the design, refer to the application cases described below.
(1) If multiple system clocks are associated with memory operation in the circuit,
clock skews are generally adjusted by assigning one BIST controller to each clock
(multiple BIST controllers as a whole). In such a case, the circuit must be
configured so as to allow clock skews to be adjusted individually for each memory
clock.
(2) Even when multiple system clocks are associated with memory operation in the
circuit, if the clocks can be integrated into one line for operation in BIST mode,
the memory BIST circuit can be configured with a single BIST controller. In
such a case, the circuit must be configured so as to allow clock skews to be
adjusted for all memory clocks in BIST mode.
(3) In cases in which multi-port memory has different clocks for the respective ports,
the clock skews must be adjusted using a multiplexer. In such a case, insert a
multiplexer for clocks other than the selected clock.
Note *3: Although the BIST circuit requires BIST_CLK as its clock input when operating
singly, BIST_CLK can normally be substituted for by the memory clock (system
clock) or other internal clock, as initialization, skew adjustment, and the like are
required. Furthermore, if the BIST circuit is configured with multiple BIST
controllers, there must be as many MBIST_GO and MBIST_DONE outputs as
the number of BIST controllers. For MBIST_EN input, however, a single input
will suffice.
*4: This circuit configuration can also include initialization of the customer’s own
circuit. If the required circuit configuration cannot be designed, contact the
sales division of Epson.
8.5.6 Other
• Memory BIST can be applied without concern for the restrictions associated with
hierarchical design, regardless of where in the customer’s circuit memory exists.
• It does not matter whether the customer’s circuit contains memory for which memory
BIST is applied or memory for which memory BIST is not applied.
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EPSON
STANDARD CELL S1K70000 SERIES
EMBEDDED ARRAY S1X70000 SERIES