S1X70000 Datasheet, PDF (358/379 Pages) Epson Company – STANDARD CELL / EMBEDDED ARRAY

Chapter 8 Circuit Design that Takes Testability into Account
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CTS Special Cell
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clock
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clock
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CRBF
ATPGEN
ATPG mode :ATPGEN=1
Figure 8-17 Processing of Internally Generated Clocks
Processing of internally generated clocks 2 (treatment of clock gating)
To avoid adding cells to the clock line for an internally generated clock, there is a
method for controlling the enable line by which the clock signal is gated. An
example is shown in Figure 8-18. Adoption of this method eliminates the need for
MUX cells placed in the clock line as in Figure 8-17, and therefore helps create a
design with relatively small clock skew.
CTS Special Cell
clock
ATPG mode :ATPGEN=1
ATPGEN
clock
CRBF
Figure 8-18 Treatment of Clock Gating
Relationship between multiple clock groups
For a design with multiple clock blocks including internally generated clocks, the
usable treatment method may be limited, depending on the relationship between
those clock blocks. Unless the circuit blocks using different clocks are physically
interconnected, there will be no problems. However, caution must be exercised if
for reasons of design specification they comprise either a false path (although
physically connected, there is no logical communication during normal operation,
or timing is not taken into consideration during logic synthesis) or a multi-cycle
path (asynchronously communicating, with several latch misses tolerated).
A
B
clock
C
Figure 8-19 (a) Example with Multiple Internally Generated Clocks
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