S1X70000 Datasheet, PDF (166/379 Pages) Epson Company – STANDARD CELL / EMBEDDED ARRAY

Chapter 5 Memory Blocks
Port-2 signals (read/write)
Input/Output Signal
Symbol
Name
CKB
Clock input
XCSB
XWEB
Chip select
Write enable
XBWEBn Byte write enable
AB0–ABn Address input
DB0–DBn Data input
YB0–YBn Data output
Functional Description
Chip select (XCSB), write enable (XWEB), byte write enable
(XBWEBn), address input (AB0–ABn), and data input (DB0–DBn)
are latched into the rising edge (Low-to-High transition) of the clock
input (CKB). Memory is activated when the latched chip-select
signal is Low. While the memory is active, data is written to
memory when the latched write-enable signal is Low or read from
memory when the signal is High. Operation finishes on the next fall
of the clock.
Latched into the rising edge of the clock input (CKB). Memory is
activated when the latched value is Low.
Latched into the rising edge of the clock input (CKB). Memory is
activated for write operation when the latched value is Low or for
read operation when the latched value is High.
Latched into the rising edge of the clock input (CKB). Each byte of
data is assigned one byte write-enable signal. Only data bytes with
Low byte write enable (XBWEBn) when write enable (XWEB) is Low
are written to memory.
XBWEB0 for DB0–DB7
XBWEB1 for DB8–DB15
XBWEB2 for DB16–DB23
XBWEB3 for DB24–DB31
Latched into the rising edge of the clock input (CKB).
The write data is latched into the rising edge of the clock input (CKB)
and written to memory cells.
During reading, the data from memory cells is output a finite access
time after the rising edge of the clock input (CKB). During writing,
the latched write data is output from these pins.
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EPSON
STANDARD CELL S1K70000 SERIES
EMBEDDED ARRAY S1X70000 SERIES