S1X70000 Datasheet, PDF (341/379 Pages) Epson Company – STANDARD CELL / EMBEDDED ARRAY

Chapter 8 Circuit Design that Takes Testability into Account
When creating the mask ROM test-state test patterns, please follow the procedure
described below in order to ensure that data can be read out from all addresses.
• Timing chart
A[n:0]
CK
XCS
Y[m :0]
Strobe
Read event
t₀
t₁
t₂
valid data
t₃
Recommended values for t₀–t₃: t₀ = 200 ns, t₁ = 20 ns, t₂ = 100 ns, t₃ = 185 ns
• Exam ple for APF form at (16 words x 4 bits)
$RATE 200000
$STROBE 185000
$RESOLUTION 0.001ns
$NODE
IA3 I 0
IA2 I 0
IA1 I 0
IA0 I 0
ICK P 20000 120000
IXCS I 0
･･･
OY3 O
OY2 O
OY1 O
OY0 O
$ENDNODE
$PATTERN
#
A A A A C X _{･･･}Y Y Y Y
#
3 2 1 0 K C _{･･･}3 2 1 0
#
S
0 0 0 0 0 P 0 _{･･･}L L H H
1 0 0 0 1 P 0 _{･･･}L L H L
2 0 0 1 0 P 0 _{･･･}L L L L
3 0 0 1 1 P 0 _{･･･}L H L L
･･･
1 2 1 1 0 0 P 0 _{･･･}H H H L
1 3 1 1 0 1 P 0 _{･･･}H H L H
1 4 1 1 1 0 P 0 _{･･･}H L H H
1 5 1 1 1 1 P 0 _{･･･}L H H H
$ENDPATTERN
Be sure to w rite all I/O pins to ensure that simulations are
perf ormed.
(1) Perf orm read operations on all addresses, based on
the read event show n above. Addresses may be
changed in any order, as desired.
(2) CK must be applied as a pulse (RZ w aveform).
There is no need to stop the clock.
(3) If there is a test-mode setup sequence, be sure to
insert it prior to event 0. (Event numbers need to be
reassigned.)
Figure 8-8 Procedure for Creating Mask ROM Test Patterns
STANDARD CELL S1K70000 SERIES
EMBEDDED ARRAY S1X70000 SERIES
EPSON
333