S1X70000 Datasheet, PDF (165/379 Pages) Epson Company – STANDARD CELL / EMBEDDED ARRAY

Chapter 5 Memory Blocks
Table 5-124 Description of High-Density-Type Dual-Port RAM Signals
Port-1 signals (read/write)
Input/Output Signal
Symbol
Name
Functional Description
CKA
Clock input
Chip select (XCSA), write enable (XWEA), byte write enable
(XBWEAn), address input (AA0–AAn), and data input (DA0–DAn)
are latched into the rising edge (Low-to-High transition) of the clock
input (CKA). Memory is activated when the latched chip-select
signal is Low. While the memory is active, data is written to
memory when the latched write-enable signal is Low or read from
memory when the signal is High. Operation finishes on the next fall
of the clock.
XCSA
Chip select
Latched into the rising edge of the clock input (CKA). Memory is
activated when the latched value is Low.
XWEA
Write enable
Latched into the rising edge of the clock input (CKA). Memory is
activated for write operation when the latched value is Low or for
read operation when the latched value is High.
XBWEAn
Byte write enable
Latched into the rising edge of the clock input (CKA). Each byte of
data is assigned one byte write-enable signal. Only data bytes with
Low byte write enable (XBWEAn) when write enable (XWEA) is Low
are written to memory.
XBWEA0 for DA0–DA7
XBWEA1 for DA8–DA15
XBWEA2 for DA16–DA23
XBWEA3 for DA24–DA31
AA0–AAn Address input
Latched into the rising edge of the clock input (CKA).
DA0–DAn Data input
The write data is latched into the rising edge of the clock input (CKA)
and written to memory cells.
YA0–YAn Data output
During reading, the data from memory cells is output a finite access
time after the rising edge of the clock input (CKA). During writing,
the latched write data is output from these pins.
STANDARD CELL S1K70000 SERIES
EMBEDDED ARRAY S1X70000 SERIES
EPSON
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