DS80C390 Datasheet, PDF (29/58 Pages) Dallas Semiconductor – Dual CAN High-Speed Microprocessor

CAN 1 MESSAGE CENTER 15
-
C1M15AR0
C1M15AR1
C1M15AR2
C1M15AR3
Reserved
CAN 1 MESSAGE 15 ARBITRATION REGISTER 0
CAN 1 MESSAGE 15 ARBITRATION REGISTER 1
CAN 1 MESSAGE 15 ARBITRATION REGISTER 2
CAN 1 MESSAGE 15 ARBITRATION REGISTER 3
C1M15F DTBYC3 DTBYC2 DTBYC1 DTBYC0 0 _{EX/ ST} MEME
C1M15D0-
C1M15D7
CAN 1 MESSAGE 15 DATA BYTE 0 - 7
Reserved
WTOE
MDME
DS80C390
xxxxF0h - F1h
xxxxF2h
xxxxF3h
xxxxF4h
xxxxF5h
xxxxF6h
xxxxF7h - FEh
xxxxFFh
Notes:
1_{The first two bytes of the CAN 1 MOVX memory address are dependent on the setting of the CMA bit}
(MCON.5) CMA=0, xxxx=00EF; CMA=1, xxxx=4011.
CAN INTERRUPTS
The DS80C390 supports 3 interrupts associated with the CAN controllers. One interrupt is dedicated to
each CAN controller, providing receive/transmit acknowledgments from each of its 15 message centers.
The remaining interrupt, the Can Bus Activity Interrupt, is used to detect CAN bus activity on the C0RX
or C1RX pins.
The message center interrupts are enabled/disabled by individual ETI (transmit) and ERI (receive) enable
bits in the corresponding Message Control Register (located in SFR memory) for each message center.
All of the message center interrupts of each CAN module are ORed together into their respective CAN
interrupt. The successful transmission or receipt of a message will set the INTRQ bit in the
corresponding Message Control Register (located in SFR memory). This bit can only be cleared via
software. In addition, the Global Interrupt Enable bit (IE.7) and the specific CAN Interrupt Enable bit,
EIE.6 (CAN0) or EIE.5 (CAN1) must be correctly set to acknowledge a message center interrupt.
Interrupt assertion of error and status conditions associated with the CAN modules is controlled by the
ERIE and STIE bits located in the CAN Control registers, C0C and C1C.
ARBITRATION AND MASKING
After a CAN module has ascertained that an incoming message is bit error-free, the identification field of
that message is then compared against one or more arbitration values to determine if they will be loaded
into a message center. Each enabled message center (see the MSRDY bit in the CAN Message Control
Register) is tested in order from 1-15. The first message center to successfully pass the test will receive
the incoming message and end the testing. The use of masking registers allows the use of more complex
identification schemes, as tests can be made based on bit patterns rather than an exact match between all
bits in the identification field and arbitration values. Each CAN processor also incorporates a set of five
masks to allow messages with different IDs to be grouped and successfully loaded into a message center;
Note that some of these masks are optional as per the bits shown in the Arbitration/Masking Feature
Summary table.
There are several possible arbitration tests, varying according to which message center is involved. If all
of the enabled tests succeed, the message is loaded into the respective message center. The most basic
test, performed on all messages, compares either 11 (CAN 2.0A) or 29 (CAN 2.0B) bits of the
identification field to the appropriate arbitration register, based on the EX/ ST bit in the CAN 0/1 Format
Register. The MEME bit (C0MxF.1 or C1MxF.1) controls whether the arbitration and ID registers are
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