DS80C390 Datasheet, PDF (17/58 Pages) Dallas Semiconductor – Dual CAN High-Speed Microprocessor

DS80C390
80C32 Idle and power down (Stop) modes, the DS80C390 provides a new Power Management Mode.
This mode allows the processor to continue instruction execution, yet at a very low speed to significantly
reduce power consumption (below even Idle mode). The DS80C390 also features several enhancements
to Stop mode that make this extremely low power mode more useful. Each of these features is discussed
in detail below.
SYSTEM CLOCK CONTROL
As mentioned previously, the microcontroller contains special clock control circuitry that simultaneously
provides maximum timing flexibility and maximum availability and economy in crystal selection. The
logical operation of the system clock divide control function is shown in Figure 2. A 3:1 multiplexer,
controlled by CD1, CD0 (PMR.7-6), selects one of three sources for the internal system clock:
§ Crystal oscillator or external clock source
§ (Crystal oscillator or external clock source) divided by 256
§ (Crystal oscillator or external clock source) frequency multiplied by 2 or 4 times.
SYSTEM CLOCK CONTROL DIAGRAM Figure 2
The system clock control circuitry generates two clock signals that are used by the microcontroller. The
internal system clock provides the timebase for timers and internal peripherals. The system clock is run
through a divide by 4 circuit to generate the machine cycle clock that provides the timebase for CPU
operations. All instructions execute in one to five machine cycles. It is important to note the distinction
between these two clock signals, as they are sometimes confused, creating errors in timing calculations.
Setting CD1, CD0 to 0 enables the frequency multiplier, either doubling or quadrupling the frequency of
the crystal oscillator or external clock source. The 4X/ 2X bit controls the multiplying factor, selecting
twice or four times the frequency when set to 0 or 1, respectively. Enabling the frequency multiplier
results in apparent instruction execution speeds of 2 or 1 clocks. Regardless of the configuration of the
frequency multiplier, the system clock of the microcontroller can never be operated faster than 40 MHz.
This means that the maximum crystal oscillator or external clock source is 10 MHz when using the 4X
setting, and 20 MHz when using the 2X setting.
The primary advantage of the clock multiplier is that it allows the microcontroller to use slower crystals
to achieve the same performance level. This reduces EMI and cost, as slower crystals are generally more
available and thus less expensive.
17 of 58
110199