DS80C390 Datasheet, PDF (24/58 Pages) Dallas Semiconductor – Dual CAN High-Speed Microprocessor

DS80C390
EXTERNAL RESET PINS
The DS80C390 has both reset input (RST) and reset output ( RSTOL ) pins. The RSTOL pin supplies an
active low Reset when the microprocessor is issued a Reset from either a high on the RST pin, a time out
of the watchdog timer, a crystal oscillator fail, or an internally detected power-fail. The timing of the
RSTOL pin is dependent on the source of the reset.
Reset Type/Source
Power-on reset
External reset
Power fail
Watchdog timer reset
Oscillator fail detect
RSTOL Duration
65536 t_CLCL (as described in Power Cycle Timing Characteristics)
< 1.25 machine cycles
65536 t_CLCL (as described in Power Cycle Timing Characteristics)
2 machine cycles
65536 t_CLCL (as described in Power Cycle Timing Characteristics)
INTERRUPTS
The microcontroller provides 16 interrupt sources with three priority levels. All interrupts, with the
exception of the Power Fail interrupt, are controlled by a series combination of individual enable bits and
a global interrupt enable EA (IE.7). Setting EA to a 1 allows individual interrupts to be enabled.
Clearing EA disables all interrupts regardless of their individual enable settings.
The three available priority levels are low, high, and highest. The highest priority level is reserved for the
Power Fail Interrupt only. All other interrupt priority levels have individual priority bits that when set to
a 1 establish the particular interrupt as high priority. In addition to the user-selectable priorities, each
interrupt also has an inherent natural priority, used to determine the priority of simultaneously occurring
interrupts. The available interrupt sources, their flags, their enables, their natural priority, and their
available priority selection bits are identified in the following table.
INTERRUPT SUMMARY Table 12
NAME
PFI
DESCRIPTION
Power Fail Interrupt
VECTOR NATURAL
PRIORITY
33h
0
FLAG BIT
PFI(WDCON.4)
ENABLE BIT PRIORITY
CONTROL BIT
EPFI(WDCON.5)
N/A
INT0
External Interrupt 0
03h
TF0
Timer 0
0Bh
INT1
External Interrupt 1
13h
1
IE0(TCON.1)**
EX0(IE.0)
PX0(IP.0)
2
TF0(TCON.5)*
ET0(IE.1)
PT0(IP.1)
3
IE1(TCON.3)**
EX1(IE.2)
PX1(IP.2)
TF1
Timer 1
1Bh
SCON0 TI0 or RI0 from serial
23h
port 0
4
TF1(TCON.7)*
ET1(IE.3)
PT1(IP.3)
5
RI_0(SCON0.0)
ES0(IE.4)
PS0(IP.4)
TI_0(SCON0.1)
TF2
Timer 2
2Bh
SCON1 TI1 or RI1 from serial 3Bh
port 1
6
TF2(T2CON.7)
ET2(IE.5)
PT2(IP.7)
7
RI_1(SCON1.0)
ES1(IE.6)
PS1(IP.6)
TI_1(SCON1.1)
INT2
External Interrupt 2
43h
8
IE2 (EXIF.4)
INT3
External Interrupt 3
4Bh
9
IE3 (EXIF.5)
INT4
External Interrupt 4
53h
10
IE4 (EXIF.6)
INT5
External Interrupt 5
5Bh
11
IE5 (EXIF.7)
C0I
CAN0 Interrupt
6Bh
12
various
C1I
CAN1 Interrupt
73h
13
various
WDTI
Watchdog Timer
63h
14
WDIF (WDCON.3)
CANBUS CAN0/1 Bus Activity
7Bh
15
various
Unless marked, all flags must be cleared by the application software.
EX2 (EIE.0)
EX3 (EIE.1)
EX4 (EIE.2)
EX5 (EIE.3)
C0IE (EIE.6)
C1IE (EIE.5)
EWDI (EIE.4)
CANBIE (EIE.7)
PX2 (EIP.0)
PX3 (EIP.1)
PX4 (EIP.2)
PX5 (EIP.3)
C0IP (EIP.6)
C1IP (EIP.5)
PWDI (EIP.4)
CANBIP (EIP.7)
* Cleared automatically by hardware when the service routine is entered.
** If edge triggered, flag is cleared automatically by hardware when the service routine is entered. If
level triggered, flag follows the state of the interrupt pin.
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