DS80C390 Datasheet, PDF (18/58 Pages) Dallas Semiconductor – Dual CAN High-Speed Microprocessor

SYSTEM CLOCK CONFIGURATION Table 10
CD1 CD0 _{4X/ 2X}
Name
Clocks/MC
00
0 Frequency Multiplier (2X)
2
00
1 Frequency Multiplier (4X)
1
0 1 N/A Reserved
1 0 N/A Divide-by-four (Default)
4
1 1 N/A Power Management Mode
1024
DS80C390
Max. External Frequency
20 MHz
10 MHz
40 MHz
40 MHz
The system clock and machine cycle rate changes one machine cycle after the instruction changing the
control bits. Note that the change will affect all aspects of system operation, including timers and baud
rates. The use of the switchback feature, described later, can eliminate many of the problems associated
with the Power Management Mode.
Changing the system clock/machine cycle clock frequency
The microcontroller incorporates a special locking sequence to ensure “glitch-free” switching of the
internal clock signals. All changes to the CD1, CD0 bits must pass through the 10 (divide-by-four) state.
For example, to change from 00 (frequency multiplier) to 11 (PMM), the software must change the bits in
the following sequence: 00 -> 10 -> 11. Attempts to switch between invalid states will fail, leaving the
CD1, CD0 bits unchanged.
The following sequence must be followed when switching to the frequency multiplier as the internal time
source. This sequence can only be performed when the device is in divide-by-four operation. The steps
must be followed in this order, although it is possible to have other instructions between them. Any
deviation from this order will cause the CD1, CD0 bits to remain unchanged. Switching from frequency
multiplier to non-multiplier mode requires no steps other than the changing of the CD1, CD0 bits.
1. Ensure that the CD1, CD0 bits are set to 10, and the RGMD (EXIF.2) bit = 0.
2. Clear the CTM (Crystal Multiplier Enable) bit.
3. Set the 4X/ 2X bit to the appropriate state.
4. Set the CTM (Crystal Multiplier Enable) bit.
5. Poll the CKRDY bit (EXIF.4), waiting until it is set to 1. This will take approximately 65536 cycles
of the external crystal or clock source.
6. Set CD1, CD0 to 00. The frequency multiplier will be engaged on the machine cycle following the
write to these bits.
OSCILLATOR FAIL DETECT
The microprocessor contains a safety mechanism called an on-chip Oscillator Fail Detect circuit. When
enabled, this circuit causes the processor to be held in reset if the oscillator frequency falls below TBD
kHz. In operation, this circuit complements the Watchdog timer. Normally, the watchdog timer is
initialized so that it will time-out and will cause a processor reset in the event that the processor loses
control. In the event of a crystal or external oscillator failure, however, the watchdog timer will not
function and there is the potential for the processor to fail in an uncontrolled state. The use of the
oscillator fail detect circuit forces the processor to a known state (i.e., reset) even if the oscillator stops.
The oscillator fail detect circuitry is enabled when software sets the enable bit OFDE (PCON.4) to a 1.
Please note that software must use a “Timed Access” procedure (described later) to write this bit. The
OFDF (PCON.5) bit will also be set to a 1 when the circuitry detects an oscillator failure, and the
processor is forced into a reset state. This bit can only be cleared to a 0 by a power fail reset or by
software. The oscillator fail detect circuitry will not be activated when the oscillator is stopped due to the
processor entering Stop mode.
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