DS80C390 Datasheet, PDF (20/58 Pages) Dallas Semiconductor – Dual CAN High-Speed Microprocessor

DS80C390
Software should not rely on a lower-priority level interrupt source to remove PMM (Switchback) when a
higher level is in service. Check the current priority service level before entering PMM. If the current
service level locks out a desired Switchback source, then it would be advisable to wait until this condition
clears before entering PMM. Alternately, software can prevent an undesired exit from PMM by
intentionally entering a low priority interrupt service level before entering PMM. This will prevent other
low priority interrupts from causing a Switchback.
Entering PMM during an ongoing serial port transmission or reception can corrupt the serial port activity.
To prevent this, a hardware lockout feature ignores changes to the clock divisor bits while the serial ports
are active. Serial port activity can be monitored via the Serial Port Activity bits located in the Status
register.
IDLE MODE
Setting the IDLE bit (PCON.0) invokes the Idle mode. Idle will leave internal clocks, serial ports and
timers running. Power consumption drops because memory is not being accessed and instructions are not
being executed. Since clocks are running, the Idle power consumption is a function of crystal frequency.
It should be approximately ½ of the operational power at a given frequency. The CPU can exit Idle mode
with any interrupt or a reset. Because Power Management Mode (PMM) consumes less power than Idle
mode, as well as leaving timers and CPU operating, Idle mode is no longer recommended for new
designs, and is included for backward software compatibility only.
STOP MODE
Setting the STOP bit of the Power Control register (PCON.1) invokes Stop mode. Stop mode is the
lowest power state (besides power off) since it turns off all internal clocking. The I_CC of a standard Stop
mode is approximately 1 µA (consult the Electrical Specifications section for full details). All processor
operation ceases at the end of the instruction that sets the STOP bit. The CPU can exit Stop mode via an
external interrupt, if enabled, or a reset condition. Internally generated interrupts (timer, serial port,
watchdog) cannot cause an exit from Stop mode because internal clocks are not active in Stop mode.
BAND-GAP SELECT
The DS80C390 provides two enhancements to Stop mode. As described below, the device provides a
band-gap reference to determine Power-fail Interrupt and Reset thresholds. The band-gap reference is
controlled by the Band-Gap Select bit, BGS (RCON.0). Setting BGS to a 1 will keep the band-gap
reference enabled during Stop mode. The default or reset condition of the bit is logic 0, which disables
the band-gap during Stop mode. This bit has no control of the reference during full power, PMM, or Idle
modes.
With the band-gap reference enabled, the Power-fail reset and interrupt are valid means for leaving Stop
mode. This allows software to detect and compensate for a power supply sag or brownout, even when in
Stop mode. In Stop mode with the band-gap enabled, I_CC will be approximately 100 µA compared with 1
µA with the band-gap disabled. If a user does not require a Power-fail Reset or Interrupt while in Stop
mode, the band-gap can remain disabled. Only the most power sensitive applications should disable the
band-gap reference in Stop mode, as this results in an uncontrolled power down condition.
RING OSCILLATOR
The second enhancement to Stop mode reduces power consumption and allows the device to restart
instantly when exiting Stop mode. The ring oscillator is an internal clock that can optionally provide the
clock source to the microcontroller when exiting Stop mode in response to an interrupt.
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