DS80C390 Datasheet, PDF (10/58 Pages) Dallas Semiconductor – Dual CAN High-Speed Microprocessor

EIE CANBIE C0IE
C1IE
MXAX
C1M1C MSRDY ETI
ERI
C1M2C MSRDY ETI
ERI
C1M3C MSRDY ETI
ERI
C1M4C MSRDY ETI
ERI
C1M5C MSRDY ETI
ERI
B
C1M6C MSRDY ETI
ERI
C1M7C MSRDY ETI
ERI
C1M8C MSRDY ETI
ERI
C1M9C MSRDY ETI
ERI
C1M10C MSRDY ETI
ERI
EIP
CANBIP C0IP
C1IP
C1M11C MSRDY ETI
ERI
C1M12C MSRDY ETI
ERI
C1M13C MSRDY ETI
ERI
C1M14C MSRDY ETI
ERI
C1M15C MSRDY ETI
ERI
*Shaded bits are Timed Access protected.
EWDI
INTRQ
INTRQ
INTRQ
INTRQ
INTRQ
INTRQ
INTRQ
INTRQ
INTRQ
INTRQ
PWDI
INTRQ
INTRQ
INTRQ
INTRQ
INTRQ
EX5
EXTRQ
EXTRQ
EXTRQ
EXTRQ
EXTRQ
EXTRQ
EXTRQ
EXTRQ
EXTRQ
EXTRQ
PX5
EXTRQ
EXTRQ
EXTRQ
EXTRQ
EXTRQ
EX4
EX3
MTRQ
MTRQ
MTRQ
MTRQ
MTRQ
ROW/TIH
ROW/TIH
ROW/TIH
ROW/TIH
ROW/TIH
MTRQ
MTRQ
MTRQ
MTRQ
MTRQ
PX4
MTRQ
MTRQ
MTRQ
MTRQ
MTRQ
ROW/TIH
ROW/TIH
ROW/TIH
ROW/TIH
ROW/TIH
PX3
ROW/TIH
ROW/TIH
ROW/TIH
ROW/TIH
ROW/TIH
EX2
DTUP
DTUP
DTUP
DTUP
DTUP
DTUP
DTUP
DTUP
DTUP
DTUP
PX2
DTUP
DTUP
DTUP
DTUP
DTUP
DS80C390
E8h
EAh
EBh
ECh
EDh
EEh
EFh
F0h
F3h
F4h
F5h
F6h
F7h
F8h
FBh
FCh
FDh
FEh
FFh
ON-CHIP ARITHMETIC ACCELERATOR
An on-chip math accelerator allows the microcontroller to perform 32- and 16-bit multiplication, division,
shifting, and normalization using dedicated hardware. Math operations are performed by sequentially
loading three special registers. The mathematical operation is determined by the sequence in which three
dedicated SFRs (MA, MB and MC) are accessed, eliminating the need for a special step to choose the
operation. The normalize function facilitates the conversion of 4-byte unsigned binary integers into
floating point format. The following table shows the operations supported by the math accelerator and
their time of execution.
ARITHMETIC ACCELERATOR EXECUTION TIMES Table 3
Operation
Result
32-bit/16-bit divide
32-bit quotient, 16-bit remainder
16-bit/16-bit divide
16-bit quotient, 16-bit remainder
16-bit/16-bit multiply
32-bit product
32-bit shift left/right
32-bit result
32-bit normalize
32-bit mantissa, 5 bit exponent
Execution Time
36 t_CLCL
24 t_CLCL
24 t_CLCL
36 t_CLCL
36 t_CLCL
The following table demonstrates the procedure to perform mathematical operations using the hardware
math accelerator. The MA and MB registers must be loaded and read in the order shown for proper
operation, although accesses to any other registers can be performed between access to the MA or MB
registers. An access to the MA, MB, or MC registers out of sequence will corrupt the operation, requiring
the software to clear the MST bit to restart the math accelerator state machine. Consult the description of
the MCNT0 SFR for details of how the shift and normalize functions operate.
10 of 58
110199