DS80C390 Datasheet, PDF (21/58 Pages) Dallas Semiconductor – Dual CAN High-Speed Microprocessor

DS80C390
During Stop mode the crystal oscillator is halted to maximize power savings. Typically 4 - 10 ms are
required for an external crystal to begin oscillating again once the device receives the exit stimulus. The
ring oscillator, by contrast, is a free-running digital oscillator that has no startup delay. The ring oscillator
feature is enabled by setting the Ring Oscillator Select bit, RGSL (EXIF.1). If enabled, the
microcontroller uses the ring oscillator as the clock source to exit Stop mode, resuming operation in less
than 100 ns. After 65536 oscillations of the external clock source (not the ring oscillator), the device will
clear the Ring Oscillator Mode bit, RGMD (EXIF.2) to indicate that the device has switched from the
ring oscillator to the external clock source.
The ring oscillator runs at approximately 10 MHz, but varies over temperature and voltage. As a result,
no serial communication or precision timing should be attempted while running from the ring oscillator
since the operating frequency is not precise. The default state exits Stop mode without using the ring
oscillator.
TIMED ACCESS PROTECTION
Selected SFR bits are critical to operation, making it desirable to protect them against an accidental write
operation. The Timed Access procedure prevents an errant processor from accidentally altering bits that
would seriously affect processor operation. The Timed Access procedure requires that the write of a
protected bit be immediately preceded by the following two instructions:
MOV 0C7h, #0AAh
MOV 0C7h, #55h
Writing an AAh followed by a 55h to the Timed Access register (location C7h), opens a three-cycle
window that allows software to modify one of the protected bits. If the instruction that seeks to modify
the protected bit is not immediately preceded by these instructions, the write will be ignored. The
protected bits are:
WDCON.6
WDCON.3
WDCON.1
WDCON.0
RCON.0
ACON.2
ACON.1-0
MCON.7-6
MCON.5
MCON.3-0
C0C.3
C1C.3
P4CNT.6
P4CNT.5-0
P5CNT.2-0
COR.7
COR.6-5
COR.4-3
COR.2-1
COR.0
POR
WDIF
EWT
RWT
BGS
SA
AM1-AM0
IDM1-IDM0
CMA
PDCE3-PDCE.0
CRST
CRST
SBCAN
P5.7-P5.5
IRDACK
C1BPR7-C1BPR6
C0BPR7-C0BPR6
COD1-COD0
CLKOE
Power-On Reset Flag
Watchdog Interrupt Flag
Watchdog Reset Enable
Reset Watchdog Timer
Band-Gap Select
Stack Address Mode
Address Mode Select bits
Internal Memory Configuration and Location bits
CAN Data Memory Assignment
Program/Data Chip Enables
CAN 0 Reset
CAN 1 Reset
Single Bus CAN
Port 4 Pin Configuration Control Bits
Configuration Control Bits
IRDA Clock Output Enable
CAN 1 Baud Rate Pre-scale Bits
CAN 0 Baud Rate Pre-scale Bits
CAN Clock Output Divide Bit 1 and Bit 0
CAN Clock Output Enable
21 of 58
110199