DS80C390 Datasheet, PDF (19/58 Pages) Dallas Semiconductor – Dual CAN High-Speed Microprocessor

POWER MANAGEMENT MODE (PMM)
Machine Cycle Rate
Full Operation
PMM
Crystal Speed
(4 clocks per (1024 clocks per
machine cycle) machine cycle)
11.0592 MHz
2.765 MHz
10.8 kHz
16 MHz
4.0 MHz
15.6 kHz
25 MHz
6.25 MHz
24.4 kHz
33 MHz
8.25 MHz
32.2 kHz
40 MHz
10.0 MHz
39.1 kHz
DS80C390
Operating Current Estimates
Full Operation
PMM
(4 clocks per (1024 clocks per
machine cycle) machine cycle)
13.1 ma
4.8 ma
17.2 ma
5.6 ma
25.7 ma
7.0 ma
32.8 ma
8.2 ma
TBD
TBD
Note that power consumption in PMM is less than Idle mode. While both modes leave the power-hungry
internal timers running, PMM runs all clocked functions such as timers at the rate of crystal divided by
1024, rather than crystal divided by 4. Even though instruction execution continues in PMM (albeit at a
reduced speed), it still consumes less power than Idle mode. As a result there is little reason to use Idle
mode in new designs.
SWITCHBACK
When enabled, the Switchback feature allows serial ports and interrupts to automatically switch back
from divide by 1024 (PMM) to divide by 4 (standard speed) operation. This feature makes it very
convenient to use the Power Management Mode in real-time applications. Software can simply set the
CD1 and CD0 clock control bits to the 4 clocks per cycle mode to exit PMM. However, the
microcontroller provides hardware alternatives for automatic Switchback to standard speed (divide by 4)
operation.
The Switchback feature is enabled by setting the SFR bit SWB (PMR.5) to a 1. Once it is enabled, and
when PMM is selected, two possible events can cause an automatic Switchback to divide by four mode.
First, if an interrupt occurs and is acknowledged, the system clock will revert from PMM to divide by
four mode. For example, if INT0 is enabled and the CPU is not servicing a higher priority interrupt, then
Switchback will occur on INT0 . However, if INT0 is not enabled or the CPU is servicing a higher
priority interrupt, then activity on INT0 will not cause Switchback to occur.
A Switchback can also occur when an enabled UART detects the start bit indicating the beginning of an
incoming serial character or when the SBUF register is loaded initiating a serial transmission. Note that a
serial character’s start bit does not generate an interrupt. The interrupt occurs only on reception of a
complete serial word. The automatic Switchback on detection of a start bit allows timer hardware to
return to divide by 4 operation (and the correct baud rate) in time for a proper serial reception or
transmission. So with Switchback enabled and a serial port enabled, the automatic switch to divide by 4
operation occurs in time to receive or transmit a complete serial character as if nothing special had
happened.
STATUS
The Status register (STATUS;C5h) provides information about interrupt and serial port activity to assist
in determining if it is possible to enter PMM. The microprocessor supports three levels of interrupt
priority: Power-fail, High, and Low. The PIP (Power-fail Priority Interrupt Status; STATUS.7), HIP
(High Priority Interrupt Status; STATUS.6), and LIP (Low Priority Interrupt Status; STATUS.5) status
bits, when set to a logic one, indicate the corresponding level is in service.
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