IBIS4-6600_09 Datasheet, PDF (9/35 Pages) Cypress Semiconductor – 6.6 MP CMOS Image Sensor

IBIS4-6600 CYII4SM6600AB
Pixel Rate
The pixel rate for this sensor is high enough to support a frame
rate greater than 75 Hz for a window size of 640 x 480 pixels
(VGA format), and 23 pixels over scan in both directions. Taking
into account a row blanking time of 7.2 µs (as baseline, refer the
following calculations), this requires a minimum pixel rate of
approximately 40 MHz. The final bandwidth of the column
amplifiers, output stage, and more is determined by external bias
resistors. Taking into account a pixel rate of 40 MHz, a full frame
rate of a little more than 5 frames/s is obtained.
The frame period of the IBIS4-6600 sensor is calculated as:
=> Frame period = (Nr. Lines * (RBT + pixel period * Nr. Pixels))
In this equation:
Nr. Lines: Number of Lines read out each frame (Y)
Nr. Pixels: Number of pixels read out each line (X)
RBT: Row Blanking Time = 7.2 µs (typical)
Pixel period: 1/40 MHz = 25 ns
Example: Read out time of the full resolution at nominal speed
(40 MHz pixel rate):
=> Frame period = (3002 * (7.2 µs + 25 ns * 2210)) = 187.5 ms
=> 5.33 fps.
Region of Interest (ROI) Read Out
Windowing is easily achieved by uploading the starting point of
the x and y-shift registers in the sensor registers (refer Table 10
on page 17). This downloaded starting point initiates the shift
register in the x and y-direction, triggered by the Y_START
(initiates the Y-shift register) and the Y_CLK (initiates the X-shift
register) pulse. The minimum step size for the x-address is 24
(only even start addresses can be chosen) and 1 for the
Y-address (every line can be addressed). The frame rate
increases in an almost linear manner when fewer pixels are read
out. Table 3 lists the achievable frame rates with ROI read out.
Table 3. Frame Rate vs. Resolution
Image Resolution (Y*X)
3002 x 2210
1501 x 1104
640 x 480
Frame Rate [frames/s]
5
14
89
Frame Readout Time [ms]
Comment
187.5
Full resolution
67
ROI read out
11
11
Output Amplifier
The output amplifier subtracts the reset and signal voltages from
each other to cancel FPN as much as possible (shown in
Figure 10). The DAC that is used for offset adjustment consists
of two DACs. One DAC is used for the main offset (DAC_raw).
The other enables fine tuning to compensate the offset difference
between the signal paths arriving at the two amplifiers A1 and A2
(DAC_fine). With the analog multiplexer, the signals S1 and S2
from the two buses can be combined to one pixel output at full
pixel rate (40 MHz). However, the two analog signals S1 and S2
can also be available on two separate output pins to allow a
higher pixel rate.
The third DAC (DAC_dark) puts its value on the buses during the
calibration of the output amplifier. In case of nondestructive
readout (no double sampling), bus1_R and bus2_R are
continuously connected to the output of the DAC_fine to provide
a reference for the signals on bus1_S and bus2_S.
The complete output amplifier can be put in standby by setting
the corresponding bit in the AMPLIFIER register.
Figure 10. Output Amplifier Architecture
bus1 S
bus1_R
bus2 S
bus2_R
+
A1
S1

analog
multiplexer
+
A2
S2

DAC_raw /
DAC_fine
Stage 1
programmable
gain amplifiers
output
drivers
1
Pixel output
Stage 2
Pixel output 2
1
Stage 3
DAC_dark
Document Number: 001-02366 Rev. *E
Page 9 of 35
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