IBIS4-6600_09 Datasheet, PDF (24/35 Pages) Cypress Semiconductor – 6.6 MP CMOS Image Sensor

IBIS4-6600 CYII4SM6600AB
Basic Frame and Line Timing
The basic frame and line timing of the IBIS4-6600 sensor is shown in Figure 23.
The pulse width of Y_CLOCK must be a minimum of one clock cycle and three clock cycles for Y_START. As long as Y_CLOCK is
applied, the sequencer stays in a suspended state.
T1 Row blanking time: During this period, the X-sequencer generates the control signals to sample the pixel signal and pixel
reset levels, and start the readout of one line. It depends on the granularity of the X-sequencer clock (see Table 12 on page 20).
T2 Pixels counted by pixel counter until the value of Nrof_pixels register is reached. Pixel_valid goes high when the internal
X_sync signal is generated. In other words, when the readout of the pixels is started. Pixel_valid goes low when the pixel
counter reaches the value loaded in the Nrof_pixels register. Eol goes high Sys_clock cycle after the falling edge of Pixel_valid.
T3 EOF goes high when the line counter reaches the value loaded in the NROF_LINES register and the line is read (PIXEL_VALID
goes low).
T4 The time delay between successive Y_CLOCK pulses needs to be equal to avoid any horizontal illumination (integration)
discrepancies in the image.
Both EOF and EOL can be tied to Y_START (EOF) and Y_CLOCK (EOL) if both signals are delayed with at least 2 SYS_CLOCK
periods to let the sensor run automatically.
Figure 23. Basic Frame and Line Timing
Document Number: 001-02366 Rev. *E
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