IBIS4-6600_09 Datasheet, PDF (26/35 Pages) Cypress Semiconductor – 6.6 MP CMOS Image Sensor

IBIS4-6600 CYII4SM6600AB
ADC Timing
Two Analog Outputs
Figure 26 shows the timing of the ADC using two analog outputs. Internally, the ADCs sample on the falling edge of the ADC_CLOCK
(in case of internal clock, the clock is half the SYS_CLOCK).
T1: Each ADC has a pipeline delay of 2 ADC_CLOCK cycles. This results in a total pipeline delay of four pixels.
Figure 26. ADC Timing using Two Analog Outputs
One Analog Output
Figure 27 shows the timing of the ADC using one analog output. Internally, the ADC samples on the falling edge of the ADC_CLOCK.
T1: The ADC has a pipeline delay of 2 ADC_CLOCK cycles.
Figure 27. ADC Timing using One Analog Output
Document Number: 001-02366 Rev. *E
Page 26 of 35
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