IBIS4-6600_09 Datasheet, PDF (29/35 Pages) Cypress Semiconductor – 6.6 MP CMOS Image Sensor

IBIS4-6600 CYII4SM6600AB
Table 15. Pin List (continued)
Pin
Pin Name
64
BS_RESET
65
BS_CLOCK
66
BS_DIN
67
BS_BUS
68
CMD_DEC
Pin Type Expected Voltage [V]
Input -
Input -
Input -
Output -
Input 0.74
Pin Description
Boundary scan (allows debugging of internal nodes): Reset.
Tie to GND if not used.
Boundary scan (allows debugging of internal nodes): Clock.
Tie to GND if not used.
Boundary scan (allows debugging of internal nodes): In. Tie
to GND if not used.
Boundary scan (allows debugging of internal nodes): Bus.
Leave floating if not used.
Biasing of X and Y decoder. Connect to V_DDD with R = 50 kΩ
and decouple to GNDD with C = 100 nF.
Note on Power On Behavior
At power on, the chip is in an undefined state. It is advised that the power on is accompanied by the assertion of the SYS_CLOCK
and a SYS_RESET pulse that puts all internal registers in their default state (all bits are set to 0). The X-shift registers are in a defined
state after the first X_SYNC, which occurs a few microseconds after the first Y_START and Y_CLOCK pulse. Before this X_SYNC,
the chip may draw more current from the analog power supply V_DDA. It is therefore favorable to have separate analog and digital
supplies. The current spike (if there are any) may also be avoided by a slower ramp up of the analog power supply or by disconnecting
the resistor on pin 3 (CMD_COLAMP) at startup.
Document Number: 001-02366 Rev. *E
Page 29 of 35
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