IBIS4-6600_09 Datasheet, PDF (23/35 Pages) Cypress Semiconductor – 6.6 MP CMOS Image Sensor

IBIS4-6600 CYII4SM6600AB
Serial to Parallel Interface
To upload the sequencer registers, a dedicated serial to parallel interface (SPI) is implemented. 16 bits (4 address bits + 12 data bits)
must be uploaded serially. The address must be uploaded first (MSB first), then the data (also MSB first).
The elementary unit cell is shown in Figure 21. Sixteen of these cells are connected in series, having a common SPI_CLK form the
entire uploadable parameter block. Dout of one cell is connected to SPI_DATA of the next cell (maximum speed is 20 MHz). The
uploaded settings on the address/data bus are loaded into the correct register of the sensor on the rising edge of signal REG_CLOCK
and become effective immediately.
Figure 21. SPI Interface
16 outputs to address/data bus
REG_CLOCK
SPI_DATA
SPI_CLK
D
Q
SPI_DATA
SPI_CLK
C
To address/data bus
REG_CLOCK
D
Q
Dout
C
SPI_CLK
E ntire uploadable addres s block
Unity C ell
SPI_DATA
REG_CLOCK
A3
A2
A1
D0
Internal register
upload
Timing Diagrams
Sequencer Control Signals
There are 3 control signals that operate the image sensor:
■ SYS_CLOCK
■ Y_CLOCK
■ Y_START
These control signals must be generated by the external system
with the following time constraints to SYS_CLOCK
(rising edge = active edge):
■ TSETUP >7.5 ns
■ THOLD > 7.5 ns
It is important that these signals are free of any glitches.
Figure 22. Relative Timing of the Three Control Signals
Document Number: 001-02366 Rev. *E
Page 23 of 35
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