IBIS4-6600_09 Datasheet, PDF (22/35 Pages) Cypress Semiconductor – 6.6 MP CMOS Image Sensor

IBIS4-6600 CYII4SM6600AB
AMPLIFIER Register
a. Gain (Bits 0:3)
The gain bits determine the gain setting of the output amplifier.
They are effective only if UNITY = 0. The gains and
corresponding bit setting are given in Table 4 on page 10.
b. Unity (Bit 4)
If UNITY = 1, the gain setting of GAIN is bypassed and the gain
amplifier is put in unity feedback.
c. One_out
If ONE_OUT = 0, the two output amplifiers are active. If
ONE_OUT = 1, the signals from the two buses are multiplexed
to output OUT1. The gain amplifier and output driver of the
second path are put in standby.
d. Standby
If STANDBY = 1, the complete output amplifier is put in standby.
This reduces the power consumption significantly.
e. Delay_clk_amp
The clock that acts on the output amplifier can be delayed to
compensate for any delay that is introduced in the path from shift
register, column selection logic, column amplifier, and buses to
the output amplifier. Setting '000' is used as a baseline.
Table 14. Added Delay by Changing the DELAY_CLK_AMP
Bit Settings
Bits
Delay [ns]
Bits
Delay [ns]
000
1.7
100
Inversion + 8.3
001
2.9
2.9
Inversion + 9.7
010
4.3
110
Inversion + 11.1
011
6.1
111
Inversion + 12.3
Dac_raw_reg and Dac_fine_reg Register
These registers determine the black reference level at the output
of the output amplifier. Bit setting 11111111 for DAC_RAW_REG
register gives the highest offset voltage; bit setting 00000000 for
DAC_RAW_REG register gives the lowest offset voltage. Ideally,
if the two output paths have no offset mismatch, the
DAC_FINE_REG register must be set to 10000000. Deviation
from this value can be used to compensate the internal mismatch
(see the section Offset DACs on page 10).
Dac_raw_dark Register
This register determines the voltage level that is put on the
internal buses during calibration of the output stage. This voltage
level is also continuously put on the reset buses in case of
nondestructive readout (as a reset level for the double sampling
FPN correction).
ADC Register
a. Standby_1 and standby_2
If only one or none of the ADCs is used, the other or both ADCs
can be put in standby by setting the bit to 1. This significantly
reduces the power consumption.
b. One
If OUT1 and OUT2 are both used and connected to ADC_IN1
and ADC_IN2 respectively, ONE must be 0 to use both ADCs
and to multiplex their output to ADC_D<9:0>. If ONE = 1, the
multiplexing is disabled.
c. Switch
If the two ADCs are used (ONE = 0) and internal pixel clock
(EXT_CLK = 0), the ADC output is delayed with one system clock
cycle if SWITCH = 1. If the two ADCs are used (ONE = 0) and
an external ADC clock (EXT_CLK = 1) is applied, the ADC output
is delayed with half ADC clock cycle if SWITCH = 1.
If only one ADC is used, the digital multiplexing is disabled by
ONE = 1, but SWITCH selects which ADC output is on
ADC_D<9:0> (SWITCH = 0: ADC_1, SWITCH = 1: ADC_2).
d. Ext_clk
If EXT_CLK = 0, the internal pixel clock (that drives the X-shift
registers and output amplifier, that is, half the system clock) is
used as input for the ADC clock. If EXT_CLK = 1, an external
clock must be applied to pin ADC_CLK_EXT (pin 46).
e. Tristate
If TRISTATE = 1, the ADC_D<9:0> outputs are in tri-state mode.
f. Delay_clk_adc
The clock that finally acts on the ADCs can be delayed to
compensate for any delay introduced in the path from the analog
outputs to the input stage of the ADCs. The same settings apply
for the delay that can be given to the clock acting on the output
amplifier (see Table 14). The best setting also depends on the
delay of the output amplifier clock and the load of the output
amplifier. It must be used to optimize the sampling moment of the
ADCs with respect to the analog pixel input signals. Setting '000'
is used as a baseline.
g. Gamma
If GAMMA is set to 0, the ADC input to output conversion is
linear, otherwise the conversion follows a 'gamma' law (more
contrast in dark parts of the window, lower contrast in the bright
parts).
h. Bitinvert
If BITINVERT = 0, 0000000000 is the conversion of the lowest
possible input voltage, otherwise the bits are inverted.
Document Number: 001-02366 Rev. *E
Page 22 of 35
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