IBIS4-6600_09 Datasheet, PDF (27/35 Pages) Cypress Semiconductor – 6.6 MP CMOS Image Sensor

IBIS4-6600 CYII4SM6600AB
Pin Information
The following table lists all the pins and their functions. There are a total of 68 pins. All pins with the same name can be connected
together.
Table 15. Pin List
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Pin Name
CMD_COL_CTU
CMD_COL
CMD_COLAMP
CMD_COLAMP_CTU
RCAL_DAC_DARK
RCAL_DAC_OUT
V_DDA
GNDA
V_DDD
GNDD
CMD_OUT_1
CMD_OUT_2
CMD_OUT_3
SPI_CLK
SPI_DATA
VDDAMP
CMD_FS_ADC
CMD_SS_ADC
CMD_AMP_ADC
GNDAMP
OUT1
ADC_IN1
VDDAMP
OUT2
ADC_IN2
V_DDD
GNDD
GNDA
Pin Type Expected Voltage [V]
Pin Description
Input 0
Biasing of columns (ctu). Decouple with 100 nF to GNDA.
Input 1.08
Biasing of columns. Connect to V_DDA with R = 10 kΩ and
decouple to GNDA with C = 100 nF.
Input 0.66
Biasing of column amplifiers. Connect to V_DDA with
R = 100 kΩ and decouple to GNDA with C = 100 nF.
Input 0.37
Biasing of column amplifiers. Connect to V_DDA with
R = 10 MΩ and decouple to GNDA with C = 100 nF.
Input 1.27 at code 128
DAC_DARK reg
Biasing of DAC for dark reference. Can be used to set output
range of DAC.
Default: Decouple to GNDA with C = 100 nF
Input 0
Biasing of DAC for output dark level. Can be used to set output
range of DAC. Default: Connect to GNDA
Power 2.5
Power 0
V_DD of analog part [2.5V]
GND (&substrate) of analog part
Power 2.5
Power 0
V_DD of digital part [2.5V]
GND (&substrate) of digital part
Input 0.78
Biasing of first stage output amplifiers. Connect to VDDAMP
with R = 50 kΩ and decouple to GNDAMP with C = 100 nF.
Input 0.97
Biasing of second stage output amplifiers. Connect to
VDDAMP with R = 25 kΩ and decouple to GNDAMP with
C = 100 nF.
Input 0.67
Biasing of third stage output amplifiers. Connect to VDDAMP
with R = 100 kΩ and decouple to GNDAMP with C = 100 nF.
Input -
Clock of digital parameter upload. Shifts on rising edge.
Input -
Serial address and data input. 16-bit word. Address first. MSB
first.
Power 2.5
Input 0.73
V_DD of analog output [2.5V] (Can be connected to V_DDA)
Biasing of first stage ADC. Connect to VDDA_ADC with
R = 50 kΩ and decouple to GNDA_ADC with C = 100 nF.
Input 0.73
Biasing of second stage ADC. Connect to VDDA_ADC with
R = 50 kΩ and decouple to GNDA_ADC.
input 0.59
Biasing of input stage ADC. Connect to VDDA_ADC with
R = 180 kΩ and decouple to GNDA_ADC with C = 100 nF.
Ground 0
GND (&substrate) of analog output
Output Black level: 1 at code 190 Analog output 1
DAC_RAW register
Input See OUT1.
Analog input ADC 1
Power
Output
2.5
V_DD of analog output [2.5V] (Can be connected to V_DDA)
Black level: 1 at code 190 Analog output 2
DAC_RAW register
Input See OUT2.
Analog input ADC 2
Power 2.5
Power 0
V_DD of digital part [2.5V]
GND (&substrate) of digital part
Power 0
GND (&substrate) of analog part
Document Number: 001-02366 Rev. *E
Page 27 of 35
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