IBIS4-6600_09 Datasheet, PDF (25/35 Pages) Cypress Semiconductor – 6.6 MP CMOS Image Sensor

IBIS4-6600 CYII4SM6600AB
Pixel Output Timing
Using Two Analog Outputs
Figure 24. Pixel Output Timing using Two Analog Outputs
The pixel signal at the OUT1 (OUT2) output becomes valid after
four SYS_CLOCK cycles when the internal X_SYNC (equal to
start of PIXEL_VALID output) appears (see Figure 24). The
PIXEL_VALID and EOL/EOF pulses can be delayed by the user
through the DELAY register.
T1: Row blanking time (see Table 12 on page 20)
T2: 4 SYS_CLOCK cycles.
Multiplexing to One Analog Output
The pixel signal at the OUT1 output becomes valid after five
SYS_CLOCK cycles when the internal X_SYNC (equal to start
of PIXEL_VALID output) appears (see Figure 25). The
PIXEL_VALID and EOL/EOF pulses can be delayed by the user
through the DELAY register.
T1: Row blanking time
T2: 5 SYS_CLOCK cycles.
Figure 25. Pixel Output Timing Multiplexing to One Analog Output
Document Number: 001-02366 Rev. *E
Page 25 of 35
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