IBIS4-6600_09 Datasheet, PDF (28/35 Pages) Cypress Semiconductor – 6.6 MP CMOS Image Sensor

IBIS4-6600 CYII4SM6600AB
Table 15. Pin List (continued)
Pin
29
30
Pin Name
V_DDA
REG_CLOCK
31
SYS_CLOCK
32
SYS_RESET
33
Y_CLK
34
Y_START
35
GNDD_ADC
36
VDDD_ADC
37
GNDA_ADC
38
VDDA_ADC
39
VHIGH_ADC
40
VLOW_ADC
41
GNDA_ADC
42
VDDA_ADC
43
GNDD_ADC
44
VDDD_ADC
45
VDD_RESET_DS
46
ADC_CLK_EXT
47
EOL
48
EOF
49
PIX_VALID
50
TEMP
51
ADC_D<9>
52
VDD_PIX
53
GND_AB
54
ADC_D<8>
55
ADC_D<7>
56
ADC_D<6>
57
ADC_D<5>
58
ADC_D<4>
59
ADC_D<3>
60
VDD_RESET
61
ADC_D<2>
62
ADC_D<1>
63
ADC_D<0>
Pin Type Expected Voltage [V]
Power 2.5
Input -
Input -
Input -
Input -
Input -
Power 0
Power 2.5
Power 0
Power 2.5
Input 1.5
Input 0.42
Power
Power
Power
Power
Power
Input
Output
0
2.5
0
2.5
2.5 (for no dual slope)
-
-
Output -
Output -
Output -
Output -
Power 2.5
Power 0
Output -
Output -
Output -
Output -
Output -
Output -
Power 2.5
Output -
Output -
Output -
Pin Description
V_DD of analog part [2.5V]
Register clock. Data on internal bus is copied to
corresponding registers on rising edge.
System clock defining the pixel rate (nominal 40 MHz, 50% ±
5% duty cycle)
Global system reset (active high)
Line clock
Start frame readout
GND (&substrate) of digital part ADC
V_DD of digital part [2.5V] ADC
GND (&substrate) of analog part
V_DD of analog part [2.5V]
ADC high reference voltage (for example, connect to
VDDA_ADC with R = 560 Ω and decouple to GNDA_ADC with
C = 100 nF)
ADC low reference voltage (for example, connect to
GNDA_ADC with R = 220 Ω and decouple to GNDA_ADC
with C = 100 nF)
GND (&substrate) of analog part
V_DD of analog part [2.5V]
GND (&substrate) of digital part ADC
V_DD of digital part [2.5V] ADC
Variable reset voltage (dual slope)
External ADC clock
Diagnostic end of line signal (produced by sequencer), can
be used as Y_CLK
Diagnostic end of frame signal (produced by sequencer), can
be used as Y_START
Diagnostic signal. High during pixel readout
Temperature measurement. Output voltage varies linearly
with temperature.
ADC data output (MSB)
V_DD of pixel core [2.5V]
Anti-blooming ground. Set to 1V for improved anti-blooming
behavior
ADC data output
ADC data output
ADC data output
ADC data output
ADC data output
ADC data output
Reset voltage [2.5V]. Highest voltage to the chip. 3.3V for
extended dynamic range or 'hard reset'.
ADC data output
ADC data output
ADC data output (LSB)
Document Number: 001-02366 Rev. *E
Page 28 of 35
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