IBIS4-6600_09 Datasheet, PDF (6/35 Pages) Cypress Semiconductor – 6.6 MP CMOS Image Sensor

IBIS4-6600 CYII4SM6600AB
Sensor Architecture and Operation
Floor Plan
Figure 4. Floor Plan
S E NS OR
IMAGE C OR E
pixel array
2210 x 3002
(excl. dark +
dummy pixels )
clk_x
s ync_x
P ixel (0,0)
column amplifiers
addres s able x-s hift regis ter + s ub-s ampling
addres s &
data bus
Dig. logic
DAC
SPI
DAC in
Dig. logic
analog output (2)
Figure 4 shows the architecture of the designed image sensor. It
consists of the pixel array, shift registers for the readout in x and
y direction, parallel analog output amplifiers, and column
amplifiers that correct for the fixed pattern noise caused by
threshold voltage nonuniformities. Reading out the pixel array
starts by applying a y clock pulse to select a new row, followed
by a calibration sequence to calibrate the column amplifiers (row
blanking time). Depending on external bias resistors and timing,
typically this sequence takes about seven seconds every line
(baseline). This sequence is necessary to remove the Fixed
Pattern Noise of the pixel and of the column amplifiers
themselves (by a Double Sampling technique). Pixels can also
be read out in a nondestructive manner.
Two DACs are added to make the offset level of the pixel values
adjustable and equal for the two output buses. A third DAC is
used to connect the buses to a stable voltage during the row
blanking period, or reset the buses continuously in case of a
nondestructive readout.
Two 10-bit ADCs running at 20 Msamples/s convert the analog
pixel values. The digital outputs are multiplexed to one digital
10-bit output at 40 Msamples/s. Note that these blocks are
electrically completely isolated from the sensor part, except for
the multiplexer, for which the settings are uploaded through the
shared address and data bus.
The x and y shift registers have a programmable starting point.
The possibilities of the starting point are limited because of
limitations imposed by subsampling requirements. The start
address is uploaded through the serial to parallel interface.
Most of the signals for the image core shown in Figure 4 are
generated on-chip by the sequencer. This sequencer also allows
running the sensor in basic modes, not fully autonomous.
Document Number: 001-02366 Rev. *E
Page 6 of 35
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