IBIS4-6600_09 Datasheet, PDF (7/35 Pages) Cypress Semiconductor – 6.6 MP CMOS Image Sensor

IBIS4-6600 CYII4SM6600AB
Pixel
Architecture
The pixel architecture is the classic three-transistor pixel, as
shown in Figure 5 The pixel is implemented using the high fill
factor technique patented by FillFactory (US patent No.
6,225,670 and others).
Figure 5. 3T Pixel Architecture
Vdd
Color Filter Array
The IBIS4-6600 can also be processed with a Bayer RGB color
pattern. Pixel (0,0) has a green filter and is situated on a
green-red row. Green1 and Green2 are separately processed
color filters and have a different spectral response. Green1 pixels
are located on a blue-green row, and green2 pixels are located
on a green-red row.
Figure 6. RGB Bayer Alignment
reset
M1
s_se_ele_lec_ct
M2
M3
output
(column)
FPN and PRNU
Fixed Pattern Noise correction is done on-chip. Raw images
taken by the sensor typically feature a residual (local) FPN of
0.35% RMS of the saturation voltage.
The Photo Response Non Uniformity (PRNU), caused by the
mismatch of photodiode node capacitances, is not corrected on
chip. Measurements indicate that the typical PRNU is about 1.5%
RMS of the signal level.
Figure 7 shows the response of the color filter array as function
of the wavelength.
Figure 7. Typical Response Curve of the RGB Filters
0.140
0.120
0.100
0.080
0.060
0.040
blue
green 1
green 2
red
m ono
0.020
0.000
400
500
600
700
800
900
1000
wavelength [nm]
Document Number: 001-02366 Rev. *E
Page 7 of 35
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