CN8380 Datasheet, PDF (68/91 Pages) Conexant Systems, Inc – integrated quad line interface unit unit for both 1.544 Mbps (T1) and 2.048 Mbps (E1) applications

3.0 Registers
3.3 Per Channel Registers
CN8380
Quad T1/E1 Line Interface
16, 26, 36, 46—Interrupt Status Register (ISR)
An Interrupt Status register (ISR) bit is latched active (high) whenever its corresponding interrupt source
[ALARM; addr n5] reports an interrupt event. All latched ISR bits are cleared when ISR is read. If the
corresponding interrupt enable [IER; addr n7] is active (high), each interrupt event forces the IRQ output pin
active (low).
ISR reports an interrupt event when an alarm status [ALARM; addr n5] changes from inactive to active
(rising edge) or from active to inactive (falling edge). The associated real-time alarm status must be read to
determine the current alarm state.
R
7
6
5
4
3
2
1
0
RALOS
RLOS
TLOC
TLOS
TSHORT
JERR
BPV
—
RALOS
RLOS
TLOC
TLOS
TSHORT
JERR
BPV
Receive Analog Loss of Signal—Indicates receiver analog loss of signal status change.
Receive Loss of Signal—Indicates receiver loss of signal status change.
Transmit Loss of Clock—Indicates transmitter loss of clock status change.
Transmit Loss of Signal—Indicates transmitter output signal fault status change.
Transmit Short Circuit—Indicates transmitter loss of analog signal status change.
Jitter Attenuator Error— Indicates JAT FIFO empty/full status change.
Bipolar Violation— Indicates a non-zero code bipolar violation status change.
17, 27, 37, 47—Interrupt Enable Register (IER)
7
6
5
4
3
2
1
RALOS
RLOS
TLOC
TLOS
TSHORT
JERR
BPV
RALOS
RLOS
TLOC
TLOS
TSHORT
JERR
BPV
Enables Receive Analog Loss Of Signal
Enables Receive Loss Of Signal
Enables Transmit Loss Of Clock
Enables Transmit Loss Of Signal
Enables Transmit Short Circuit
Enables Jitter Attenuator Error
Enables Bipolar Violation
R/W
0
—
3-16
Conexant
N8380DSA
Advance Information
4/21/99