CN8380 Datasheet, PDF (18/91 Pages) Conexant Systems, Inc – integrated quad line interface unit unit for both 1.544 Mbps (T1) and 2.048 Mbps (E1) applications

1.0 Pin Descriptions
CN8380
Quad T1/E1 Line Interface
Table 1-1. Hardware Signal Definitions (2 of 5)
Pin Label
Signal Name I/O
Definition
XTIP[1:4]
XRING[1:4]
Transmit Tip
Transmit Ring
O Complementary AMI transmitter line outputs for direct connection to
transmit transformer. Optionally, both outputs are three-stated when XOE
is high.
Clock Rate Adapter (CLAD)
CLADI
REFCKI
CLK32
CLK1544
CLK2048
CLADO
CLAD Input
Reference Clock
32 MHz Clock
Output
T1 Clock Output
E1 Clock Output
CLAD Output
I CLAD input timing reference used to phase/frequency lock the CLAD
outputs to an input clock frequency selected in the range of 8 kHz to
32,768 kHz [CLAD_CR; addr 02]. Systems which do not use CLADI should
connect CLADI to ground. In Hardware Mode, the CLAD timing reference
automatically switches to internal free-run operation if clock edges are not
detected on CLADI pin.
I System must apply a 10 MHz ± 50 ppm (E1) or + 32 ppm (T1) clock signal
to act as the frequency reference for the internal numerically controlled
oscillator (NCO). REFCKI determines the frequency accuracy and stability
of the CLAD output clocks when operating in free-run mode [CLAD_CR;
addr 02]. REFCKI is the baseband reference for all CLAD/JAT functions
and is used internally to generate clocks of various frequency locked to a
selected receive or external clock.
Note: REFCKI is always required.
O Fixed rate 32.768 MHz clock output provided by the CLAD. May be used
by framers, such as the CN8398 octal T1/E1 framer, to provide system
timing reference.
O Fixed rate 1.544 MHz T1 line rate clock output provided by the CLAD. May
be used for TCLK or TACKI clock sources. This clock is locked to the
selected CLAD timing reference.
O Fixed rate 2.048 MHz E1 line rate clock output provided by the CLAD. May
be used for TCLK or EACKI clock sources. This clock is locked to the
selected CLAD timing reference.
O In Hardware Mode, CLADO is a fixed rate 8 kHz clock output provided by
the CLAD. In Host Mode, CLADO may be configured to operate at one of
14 different clock frequencies [CSEL; addr 03] that include T1 or E1 line
rates. CLADO is typically programmed to supply system clocks that are
phase-locked to the selected receive or CLAD timing reference [CLAD_CR;
addr 02].
Hardware Control Signals
HM
RAWMD[1:4]
Hardware Mode
Raw Mode
I^{P A high on HM places the device in Hardware Mode, enabling all hardware}
control pin functions. A low on HM places the device in Host Mode,
disabling some hardware-mode-only pin functions and enabling the serial
port signals on the dual function pins listed below. The serial port signals
allow serial host access to the device registers. Refer to the Host Serial
Control Signals section of this table.
JSEL(1) / CS
JDIR / SCLK
JSEL(2) / SDI
JATERR(1) / SDO
I^{P Low selects receiver Raw mode. Applicable only in Hardware Mode. In}
Raw mode, RPOSO and RNEGO represent the data slicer outputs and
RCKO is the logical OR of RPOSO and RNEGO.
1-6
Conexant
N8380DSA
Advance Information