CN8380 Datasheet, PDF (19/91 Pages) Conexant Systems, Inc – integrated quad line interface unit unit for both 1.544 Mbps (T1) and 2.048 Mbps (E1) applications

CN8380
Quad T1/E1 Line Interface
1.0 Pin Descriptions
Table 1-1. Hardware Signal Definitions (3 of 5)
Pin Label
Signal Name I/O
Definition
RESET
UNIPOLAR
ZCS
CLK_POL
PTS(2:0)
HTERM
IRQ
JSEL(2:0)
JDIR
JATERR[1:4]
Hardware Reset
Unipolar Mode
Select
Zero Code
Suppression
Select
Rx Clock Polarity
Select
Transmit Pulse
Template Select
Transmitter
Hardware
Termination
Interrupt Request
Jitter Attenuator
Select
Jitter Attenuator
Direction
Jitter Attenuator
Error
I^{P Active low asynchronous hardware reset. A falling edge forces registers to}
their default, power-up state. Output pins are forced to the high impedance
state while RESET is asserted. RESET is not mandatory at power-up
because an internal power-on reset circuit performs an identical function.
I^{P Applicable only in Hardware Mode. A high signal on UNIPOLAR configures}
all RPOSO outputs and TPOSI inputs to operate with unipolar, NRZ-
formatted data. In this mode, RNEGO reports non-ZCS BPVs and TNEGI is
not used. A low signal on UNIPOLAR configures all channels’
RPOSO/RNEGO and TPOSI/TNEGI interfaces to operate with bipolar,
dual-rail, NRZ formatted data.
I^{P Applicable only in Hardware Mode. A high signal on ZCS enables the}
transmit ZCS encoder and the receive ZCS decoder if unipolar mode is
enabled (UNIPOLAR = 1). In Bipolar Mode (UNIPOLAR = 0), the ZCS
encoder and decoder are disabled and ZCS is ignored.
I^{P Applicable only in Hardware Mode. High sets RPOSO/RNEGO to be output}
on the falling edge of RCKO. Low sets RPOSO/RNEGO to be output on the
rising edge of RCKO
I^{P Applicable only in Hardware Mode. The PTS(2:0) control bus selects the}
transmit pulse template and the line rate (T1 or E1) globally for all
channels. Refer to the description of HTERM in this table and to the
transmit pulse configurations in Table 2-3.
I^{P Applicable only in Hardware Mode. If an external transmit termination}
resistor is used to meet return loss specifications; a transformer with a 1:2
turns ratio is used, and HTERM is set high to allow the transmitter to
compensate for the increased load. Refer to the Transmitter section of this
table and Tables 2-4 through 2-8 for transmitter termination configuration
options.
O^{D Active low, open drain output. In Host Mode, IRQ indicates one or more}
pending interrupt requests ([ISR; addr n6] and [CSTAT; addr 06]). In
Hardware Mode, IRQ is the logical NOR of the four internal transmitter
driver performance monitor outputs.
I^{P Applicable only in Hardware Mode. The JSEL and JDIR pins determine the}
JAT configuration. JSEL(2:0) enables and selects the JAT depth as shown
in the table below. SDI/JSEL(2) and CS /JSEL(1) are dual function pins.
JSEL(2:0)
000
001
010
011
100
111
JAT Mode
8 bits
16 bits
32 bits
64 bits
128 bits
Disable JAT
I^{P Applicable only in Hardware Mode. JDIR determines the path in which the}
JAT is inserted. If JDIR is low, the JAT (if enabled) is placed in the receive
path; if high, the JAT (if enabled) is placed in the transmit path. Refer to
the description for JSEL(2:0). SCLK/JDIR is a dual function pin.
O Applicable only in Hardware Mode. A high on JATERR indicates an
overflow or underflow error in the jitter attenuator elastic store.
JATERR(1) / SDO is a dual function pin.
N8380DSA
Conexant
1-7
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