CN8380 Datasheet, PDF (33/91 Pages) Conexant Systems, Inc – integrated quad line interface unit unit for both 1.544 Mbps (T1) and 2.048 Mbps (E1) applications

CN8380
Quad T1/E1 Line Interface
2.4.1.2 Unipolar Mode
2.0 Circuit Description
2.4 Transmitter
enabled per channel by writing a 0 to register bit UNIPOLAR [RLIU_CR;
addr n1].
In unipolar mode, TPOSI is replaced with TDATI and accepts unipolar NRZ-
formatted transmit data. TNEGI is not used in this mode. A high on TDATI
causes an AMI pulse to be transmitted to the line. In this mode, the TZCS encoder
can be enabled to provide B8ZS or HDB3 zero code suppression. In Hardware
Mode, unipolar operation is enabled globally for all channels by pulling the
UNIPOLAR pin high. In Host Mode, unipolar operation is enabled per channel
by writing a 1 to register bit UNIPOLAR [RLIU_CR; addr n1].
2.4.2 TZCS Encoder
If enabled, the TZCS encoder encodes unipolar transmit data on TDATI with
B8ZS (T1) or HDB3 (E1) line coding. In T1 mode, eight consecutive 0s are
replaced with 000VB0VB; and in E1 mode, four consecutive 0s are replaced with
X00V; where B is a normal AMI pulse, V is a bipolar violation, and X is a Don't
Care. These are standard T1 and E1 line code options.
ZCS encoding (and decoding) can be enabled only if the digital interface
mode is unipolar. In Host Mode, TZCS encoding (and RZCS decoding) is enabled
for each channel by setting the ZCS [RLIU_CR; addr n1] register bit to 1. In
Hardware Mode, ZCS encoding/decoding is controlled globally for all channels
by pulling the ZCS pin high. For the Hardware Mode pin definition, refer to
Table 1-1.
2.4.3 Transmit Jitter Attenuator
Transmit data from the TZCS encoder can be routed to the JAT before going to
the AIS Generator. The JAT attenuates clock and data jitter from the transmit
inputs or from the receiver if Remote Line Loopback (RLL) is active. The JAT
can be placed in the receive path or transmit path, but not both simultaneously. If
the JAT is placed in the transmit path, the jitter attenuated clock becomes the
transmit clock for downstream circuits.
In Host Mode, the JAT is configured for each channel independently and is
put in the transmit path by setting the JEN register bit to 1 and the JDIR register
bit to 0 [JAT_CR; addr n0]. In Hardware Mode, the JAT is configured for all
channels globally using the JSEL(2:0) and JDIR pins. For pin definitions, refer to
Chapter 1.0, Pin Descriptions; for JAT transfer characteristics, refer to Figure 2-9;
and for more information on loopbacks, refer to Section 2.5, Loopbacks.
2.4.4 All 1s AIS Generator
The transmit data can be replaced with unframed all 1s for transmitting the alarm
indication signal (AIS). This includes replacing data supplied from
TPOSI[n]/TNEGI[n] pins and from the receiver during RLL. AIS transmission
does not affect transmit data that is looped back to the receiver during Local
Digital Loopback (LDL). This allows LDL to be active simultaneously with the
transmission of AIS. AIS is used to maintain a valid signal on the line and to
inform downstream equipment that the transmit data source has been lost. AIS
transmission can be done manually or automatically when loss of transmit clock
is detected. A clock monitor circuit allows manual or automatic switching of the
transmit clock to an alternate AIS clock.
N8380DSA
Conexant
2-11
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