CN8380 Datasheet, PDF (51/91 Pages) Conexant Systems, Inc – integrated quad line interface unit unit for both 1.544 Mbps (T1) and 2.048 Mbps (E1) applications

CN8380
Quad T1/E1 Line Interface
2.0 Circuit Description
2.8 Test Access Port (JTAG)
2.8 Test Access Port (JTAG)
The CN8380 incorporates printed circuit board testability circuits in compliance
with IEEE Std P1149.1a–1993, IEEE Standard Test Access Port and
Boundary–Scan Architecture, commonly known as JTAG (Joint Test Action
Group).
The JTAG includes a test access port (TAP) and several data registers. The
TAP provides a standard interface through which instructions and test data are
communicated. A Boundary Scan Description Language (BSDL) file for the
CN8380 is available from the factory upon request.
The test access port consists of the TRST, TDI, TCK, TMS, and TDO pins. An
internal power on reset circuit or the TRST resets the JTAG port.
2.8.1 Instructions
In addition to the required BYPASS, SAMPLE/PRELOAD, and EXTEST
instructions, IDCODE instruction is supported. There are also two private
instructions. Table 2-13 lists the JTAG instructions and their codes.
Table 2-13. JTAG Instructions
Instructions
Code
BYPASS
SAMPLE/PRELOAD
EXTEST
IDCODE
1111
0001
0000
0010
2.8.2 Device Identification Register
The JTAG ID register consists of a 4-bit version, a 16-bit part number, and an
11-bit manufacturer number as listed in Table 2-14.
Table 2-14. Device Identification JTAG Register
Version
Part Number
Manufacturer ID
0 0 0 0 1 0 0 0 0 0 1 11 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 1 0 1
0x0
0x8380
0x0D6
4 Bits
16 Bits
11 Bits
N8380DSA
Conexant
2-29
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